PCI: rcar: Convert to MSI domains
In anticipation of the removal of the msi_controller structure, convert the Rcar host controller driver to MSI domains. We end-up with the usual two domain structure, the top one being a generic PCI/MSI domain, the bottom one being Rcar-specific and handling the actual HW interrupt allocation. Link: https://lore.kernel.org/r/20210330151145.997953-4-maz@kernel.org Tested-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> [lorenzo.pieralisi@arm.com: merged fix https://lore.kernel.org/linux-pci/87y2e2p9wk.wl-maz@kernel.org] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Marc Zyngier
Lorenzo Pieralisi
parent
93cd1bb486
commit
83ed8d4fa6
@ -58,7 +58,6 @@ config PCIE_RCAR_HOST
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bool "Renesas R-Car PCIe host controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCI_MSI_ARCH_FALLBACKS
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help
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Say Y here if you want PCIe controller support on R-Car SoCs in host
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mode.
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@ -35,17 +35,12 @@
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struct rcar_msi {
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DECLARE_BITMAP(used, INT_PCI_MSI_NR);
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struct irq_domain *domain;
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struct msi_controller chip;
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struct mutex lock;
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struct mutex map_lock;
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spinlock_t mask_lock;
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int irq1;
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int irq2;
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};
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static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
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{
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return container_of(chip, struct rcar_msi, chip);
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}
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/* Structure representing the PCIe interface */
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struct rcar_pcie_host {
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struct rcar_pcie pcie;
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@ -55,6 +50,11 @@ struct rcar_pcie_host {
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int (*phy_init_fn)(struct rcar_pcie_host *host);
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};
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static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi)
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{
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return container_of(msi, struct rcar_pcie_host, msi);
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}
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static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
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{
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unsigned int shift = BITS_PER_BYTE * (where & 3);
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@ -291,8 +291,6 @@ static int rcar_pcie_enable(struct rcar_pcie_host *host)
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bridge->sysdata = host;
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bridge->ops = &rcar_pcie_ops;
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if (IS_ENABLED(CONFIG_PCI_MSI))
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bridge->msi = &host->msi.chip;
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return pci_host_probe(bridge);
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}
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@ -472,42 +470,6 @@ static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host)
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return err;
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}
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static int rcar_msi_alloc(struct rcar_msi *chip)
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{
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int msi;
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mutex_lock(&chip->lock);
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msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
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if (msi < INT_PCI_MSI_NR)
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set_bit(msi, chip->used);
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else
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msi = -ENOSPC;
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mutex_unlock(&chip->lock);
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return msi;
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}
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static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
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{
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int msi;
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mutex_lock(&chip->lock);
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msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
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order_base_2(no_irqs));
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mutex_unlock(&chip->lock);
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return msi;
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}
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static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
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{
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mutex_lock(&chip->lock);
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clear_bit(irq, chip->used);
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mutex_unlock(&chip->lock);
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}
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static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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{
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struct rcar_pcie_host *host = data;
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@ -526,18 +488,13 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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unsigned int index = find_first_bit(®, 32);
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unsigned int msi_irq;
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/* clear the interrupt */
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rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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msi_irq = irq_find_mapping(msi->domain, index);
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msi_irq = irq_find_mapping(msi->domain->parent, index);
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if (msi_irq) {
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if (test_bit(index, msi->used))
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generic_handle_irq(msi_irq);
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else
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dev_info(dev, "unhandled MSI\n");
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generic_handle_irq(msi_irq);
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} else {
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/* Unknown MSI, just clear it */
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dev_dbg(dev, "unexpected MSI\n");
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rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR);
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}
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/* see if there's any more pending in this vector */
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@ -547,150 +504,169 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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static void rcar_msi_top_irq_ack(struct irq_data *d)
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{
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struct rcar_msi *msi = to_rcar_msi(chip);
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struct rcar_pcie_host *host = container_of(chip, struct rcar_pcie_host,
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msi.chip);
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struct rcar_pcie *pcie = &host->pcie;
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struct msi_msg msg;
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unsigned int irq;
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int hwirq;
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hwirq = rcar_msi_alloc(msi);
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if (hwirq < 0)
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return hwirq;
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irq = irq_find_mapping(msi->domain, hwirq);
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if (!irq) {
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rcar_msi_free(msi, hwirq);
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return -EINVAL;
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}
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irq_set_msi_desc(irq, desc);
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msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
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msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
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msg.data = hwirq;
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pci_write_msi_msg(irq, &msg);
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return 0;
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irq_chip_ack_parent(d);
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}
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static int rcar_msi_setup_irqs(struct msi_controller *chip,
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struct pci_dev *pdev, int nvec, int type)
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static void rcar_msi_top_irq_mask(struct irq_data *d)
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{
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struct rcar_msi *msi = to_rcar_msi(chip);
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struct rcar_pcie_host *host = container_of(chip, struct rcar_pcie_host,
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msi.chip);
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struct rcar_pcie *pcie = &host->pcie;
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struct msi_desc *desc;
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struct msi_msg msg;
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unsigned int irq;
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void rcar_msi_top_irq_unmask(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip rcar_msi_top_chip = {
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.name = "PCIe MSI",
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.irq_ack = rcar_msi_top_irq_ack,
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.irq_mask = rcar_msi_top_irq_mask,
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.irq_unmask = rcar_msi_top_irq_unmask,
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};
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static void rcar_msi_irq_ack(struct irq_data *d)
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{
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struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
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struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
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/* clear the interrupt */
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rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR);
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}
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static void rcar_msi_irq_mask(struct irq_data *d)
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{
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struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
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struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&msi->mask_lock, flags);
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value = rcar_pci_read_reg(pcie, PCIEMSIIER);
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value &= ~BIT(d->hwirq);
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rcar_pci_write_reg(pcie, value, PCIEMSIIER);
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spin_unlock_irqrestore(&msi->mask_lock, flags);
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}
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static void rcar_msi_irq_unmask(struct irq_data *d)
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{
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struct rcar_msi *msi = irq_data_get_irq_chip_data(d);
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struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&msi->mask_lock, flags);
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value = rcar_pci_read_reg(pcie, PCIEMSIIER);
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value |= BIT(d->hwirq);
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rcar_pci_write_reg(pcie, value, PCIEMSIIER);
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spin_unlock_irqrestore(&msi->mask_lock, flags);
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}
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static int rcar_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct rcar_msi *msi = irq_data_get_irq_chip_data(data);
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struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
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msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
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msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
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msg->data = data->hwirq;
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}
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static struct irq_chip rcar_msi_bottom_chip = {
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.name = "Rcar MSI",
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.irq_ack = rcar_msi_irq_ack,
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.irq_mask = rcar_msi_irq_mask,
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.irq_unmask = rcar_msi_irq_unmask,
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.irq_set_affinity = rcar_msi_set_affinity,
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.irq_compose_msi_msg = rcar_compose_msi_msg,
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};
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static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct rcar_msi *msi = domain->host_data;
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unsigned int i;
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int hwirq;
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int i;
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/* MSI-X interrupts are not supported */
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if (type == PCI_CAP_ID_MSIX)
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return -EINVAL;
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mutex_lock(&msi->map_lock);
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WARN_ON(!list_is_singular(&pdev->dev.msi_list));
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desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
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hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs));
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mutex_unlock(&msi->map_lock);
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hwirq = rcar_msi_alloc_region(msi, nvec);
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if (hwirq < 0)
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return -ENOSPC;
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irq = irq_find_mapping(msi->domain, hwirq);
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if (!irq)
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return -ENOSPC;
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for (i = 0; i < nvec; i++) {
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/*
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* irq_create_mapping() called from rcar_pcie_probe() pre-
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* allocates descs, so there is no need to allocate descs here.
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* We can therefore assume that if irq_find_mapping() above
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* returns non-zero, then the descs are also successfully
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* allocated.
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*/
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if (irq_set_msi_desc_off(irq, i, desc)) {
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/* TODO: clear */
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return -EINVAL;
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}
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}
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desc->nvec_used = nvec;
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desc->msi_attrib.multiple = order_base_2(nvec);
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msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
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msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
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msg.data = hwirq;
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pci_write_msi_msg(irq, &msg);
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&rcar_msi_bottom_chip, domain->host_data,
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handle_edge_irq, NULL, NULL);
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return 0;
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}
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static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct rcar_msi *msi = to_rcar_msi(chip);
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struct irq_data *d = irq_get_irq_data(irq);
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct rcar_msi *msi = domain->host_data;
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rcar_msi_free(msi, d->hwirq);
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mutex_lock(&msi->map_lock);
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bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs));
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mutex_unlock(&msi->map_lock);
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}
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static struct irq_chip rcar_msi_irq_chip = {
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.name = "R-Car PCIe MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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static const struct irq_domain_ops rcar_msi_domain_ops = {
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.alloc = rcar_msi_domain_alloc,
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.free = rcar_msi_domain_free,
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};
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static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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static struct msi_domain_info rcar_msi_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI),
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.chip = &rcar_msi_top_chip,
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};
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static int rcar_allocate_domains(struct rcar_msi *msi)
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{
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irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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struct rcar_pcie *pcie = &msi_to_host(msi)->pcie;
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struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
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struct irq_domain *parent;
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parent = irq_domain_create_linear(fwnode, INT_PCI_MSI_NR,
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&rcar_msi_domain_ops, msi);
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if (!parent) {
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dev_err(pcie->dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
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msi->domain = pci_msi_create_irq_domain(fwnode, &rcar_msi_info, parent);
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if (!msi->domain) {
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dev_err(pcie->dev, "failed to create MSI domain\n");
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irq_domain_remove(parent);
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return -ENOMEM;
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}
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = rcar_msi_map,
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};
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static void rcar_pcie_unmap_msi(struct rcar_pcie_host *host)
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static void rcar_free_domains(struct rcar_msi *msi)
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{
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struct rcar_msi *msi = &host->msi;
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int i, irq;
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for (i = 0; i < INT_PCI_MSI_NR; i++) {
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irq = irq_find_mapping(msi->domain, i);
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if (irq > 0)
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irq_dispose_mapping(irq);
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}
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struct irq_domain *parent = msi->domain->parent;
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irq_domain_remove(msi->domain);
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}
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static void rcar_pcie_hw_enable_msi(struct rcar_pcie_host *host)
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{
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struct rcar_pcie *pcie = &host->pcie;
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struct device *dev = pcie->dev;
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struct resource res;
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if (WARN_ON(of_address_to_resource(dev->of_node, 0, &res)))
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return;
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/* setup MSI data target */
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rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
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rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
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/* enable all MSI interrupts */
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rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
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irq_domain_remove(parent);
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}
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static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
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@ -698,29 +674,24 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
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struct rcar_pcie *pcie = &host->pcie;
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struct device *dev = pcie->dev;
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struct rcar_msi *msi = &host->msi;
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int err, i;
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struct resource res;
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int err;
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mutex_init(&msi->lock);
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mutex_init(&msi->map_lock);
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spin_lock_init(&msi->mask_lock);
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msi->chip.dev = dev;
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msi->chip.setup_irq = rcar_msi_setup_irq;
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msi->chip.setup_irqs = rcar_msi_setup_irqs;
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msi->chip.teardown_irq = rcar_msi_teardown_irq;
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err = of_address_to_resource(dev->of_node, 0, &res);
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if (err)
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return err;
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|
||||
msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
|
||||
&msi_domain_ops, &msi->chip);
|
||||
if (!msi->domain) {
|
||||
dev_err(dev, "failed to create IRQ domain\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (i = 0; i < INT_PCI_MSI_NR; i++)
|
||||
irq_create_mapping(msi->domain, i);
|
||||
err = rcar_allocate_domains(msi);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Two irqs are for MSI, but they are also used for non-MSI irqs */
|
||||
err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
|
||||
IRQF_SHARED | IRQF_NO_THREAD,
|
||||
rcar_msi_irq_chip.name, host);
|
||||
rcar_msi_bottom_chip.name, host);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to request IRQ: %d\n", err);
|
||||
goto err;
|
||||
@ -728,19 +699,26 @@ static int rcar_pcie_enable_msi(struct rcar_pcie_host *host)
|
||||
|
||||
err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
|
||||
IRQF_SHARED | IRQF_NO_THREAD,
|
||||
rcar_msi_irq_chip.name, host);
|
||||
rcar_msi_bottom_chip.name, host);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to request IRQ: %d\n", err);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* setup MSI data target */
|
||||
rcar_pcie_hw_enable_msi(host);
|
||||
/* disable all MSIs */
|
||||
rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
|
||||
|
||||
/*
|
||||
* Setup MSI data target using RC base address address, which
|
||||
* is guaranteed to be in the low 32bit range on any RCar HW.
|
||||
*/
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
rcar_pcie_unmap_msi(host);
|
||||
rcar_free_domains(msi);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -754,7 +732,7 @@ static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host)
|
||||
/* Disable address decoding of the MSI interrupt, MSIFE */
|
||||
rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
|
||||
|
||||
rcar_pcie_unmap_msi(host);
|
||||
rcar_free_domains(&host->msi);
|
||||
}
|
||||
|
||||
static int rcar_pcie_get_resources(struct rcar_pcie_host *host)
|
||||
@ -1007,8 +985,17 @@ static int __maybe_unused rcar_pcie_resume(struct device *dev)
|
||||
dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
|
||||
|
||||
/* Enable MSI */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||||
rcar_pcie_hw_enable_msi(host);
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
struct resource res;
|
||||
u32 val;
|
||||
|
||||
of_address_to_resource(dev->of_node, 0, &res);
|
||||
rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR);
|
||||
rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR);
|
||||
|
||||
bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR);
|
||||
rcar_pci_write_reg(pcie, val, PCIEMSIIER);
|
||||
}
|
||||
|
||||
rcar_pcie_hw_enable(host);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user