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Add dcr_host_t.base in dcr_read()/dcr_write()

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Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we
can save them the trouble and do it in dcr_read()/dcr_write().

As some background to why we just went through all this jiggery-pokery,
benh sayeth:

 Initially the goal of the dcr_read/dcr_write routines was to operate like
 mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx
 hardware, indirect DCR access is a pain (goes through a table of
 instructions) and it's useful to have the compiler resolve an absolute DCR
 inline.

 We decided that wasn't worth the API bastardisation since most places
 where absolute DCR values are used are low level 4xx-only code which may
 as well continue using mfdcr/mtdcr, while the new API is designed for
 device "instances" that can exist on 4xx and Axon type platforms and may
 be located at variable DCR offsets.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Michael Ellerman 2007-10-15 19:34:36 +10:00 committed by Jeff Garzik
parent 0f18e719dc
commit 83f34df4e7
6 changed files with 12 additions and 12 deletions
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4
arch/powerpc/platforms/cell/axon_msi.c
View File

@ -77,12 +77,12 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{ {
pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
dcr_write(msic->dcr_host, msic->dcr_host.base + dcr_n, val); dcr_write(msic->dcr_host, dcr_n, val);
} }
static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n)
{ {
return dcr_read(msic->dcr_host, msic->dcr_host.base + dcr_n); return dcr_read(msic->dcr_host, dcr_n);
} }
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)

4
arch/powerpc/sysdev/mpic.c
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@ -156,7 +156,7 @@ static inline u32 _mpic_read(enum mpic_reg_type type,
switch(type) { switch(type) {
#ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR
case mpic_access_dcr: case mpic_access_dcr:
return dcr_read(rb->dhost, rb->dhost.base + reg); return dcr_read(rb->dhost, reg);
#endif #endif
case mpic_access_mmio_be: case mpic_access_mmio_be:
return in_be32(rb->base + (reg >> 2)); return in_be32(rb->base + (reg >> 2));
@ -173,7 +173,7 @@ static inline void _mpic_write(enum mpic_reg_type type,
switch(type) { switch(type) {
#ifdef CONFIG_PPC_DCR #ifdef CONFIG_PPC_DCR
case mpic_access_dcr: case mpic_access_dcr:
return dcr_write(rb->dhost, rb->dhost.base + reg, value); return dcr_write(rb->dhost, reg, value);
#endif #endif
case mpic_access_mmio_be: case mpic_access_mmio_be:
return out_be32(rb->base + (reg >> 2), value); return out_be32(rb->base + (reg >> 2), value);

4
drivers/net/ibm_emac/ibm_emac_mal.h
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@ -208,12 +208,12 @@ struct ibm_ocp_mal {
static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg) static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
{ {
return dcr_read(mal->dcrhost, mal->dcrhost.base + reg); return dcr_read(mal->dcrhost, reg);
} }
static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val) static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
{ {
dcr_write(mal->dcrhost, mal->dcrhost.base + reg, val); dcr_write(mal->dcrhost, reg, val);
} }
/* Register MAL devices */ /* Register MAL devices */

4
drivers/net/ibm_newemac/mal.h
View File

@ -212,12 +212,12 @@ struct mal_instance {
static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg) static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg)
{ {
return dcr_read(mal->dcr_host, mal->dcr_host.base + reg); return dcr_read(mal->dcr_host, reg);
} }
static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val) static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val)
{ {
dcr_write(mal->dcr_host, mal->dcr_host.base + reg, val); dcr_write(mal->dcr_host, reg, val);
} }
/* Register MAL devices */ /* Register MAL devices */

4
include/asm-powerpc/dcr-mmio.h
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@ -37,12 +37,12 @@ extern void dcr_unmap(dcr_host_t host, unsigned int dcr_n, unsigned int dcr_c);
static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n) static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
{ {
return in_be32(host.token + dcr_n * host.stride); return in_be32(host.token + ((host.base + dcr_n) * host.stride));
} }
static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value) static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
{ {
out_be32(host.token + dcr_n * host.stride, value); out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
} }
extern u64 of_translate_dcr_address(struct device_node *dev, extern u64 of_translate_dcr_address(struct device_node *dev,

4
include/asm-powerpc/dcr-native.h
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@ -30,8 +30,8 @@ typedef struct {
#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) #define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) })
#define dcr_unmap(host, dcr_n, dcr_c) do {} while (0) #define dcr_unmap(host, dcr_n, dcr_c) do {} while (0)
#define dcr_read(host, dcr_n) mfdcr(dcr_n) #define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
#define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value) #define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
/* Device Control Registers */ /* Device Control Registers */
void __mtdcr(int reg, unsigned int val); void __mtdcr(int reg, unsigned int val);