EDAC/i10nm: Use readl() to access MMIO registers
Instead of raw access, use readl() to access MMIO registers of
memory controller to avoid possible compiler re-ordering.
Fixes: d4dc89d069
("EDAC, i10nm: Add a driver for Intel 10nm server processors")
Cc: <stable@vger.kernel.org>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
parent
41545aabff
commit
83ff51c4e3
@ -6,6 +6,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include <asm/mce.h>
|
||||
@ -19,14 +20,16 @@
|
||||
#define i10nm_printk(level, fmt, arg...) \
|
||||
edac_printk(level, "i10nm", fmt, ##arg)
|
||||
|
||||
#define I10NM_GET_SCK_BAR(d, reg) \
|
||||
#define I10NM_GET_SCK_BAR(d, reg) \
|
||||
pci_read_config_dword((d)->uracu, 0xd0, &(reg))
|
||||
#define I10NM_GET_IMC_BAR(d, i, reg) \
|
||||
pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
|
||||
#define I10NM_GET_DIMMMTR(m, i, j) \
|
||||
(*(u32 *)((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4))
|
||||
readl((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4)
|
||||
#define I10NM_GET_MCDDRTCFG(m, i, j) \
|
||||
(*(u32 *)((m)->mbase + 0x20970 + (i) * 0x4000 + (j) * 4))
|
||||
readl((m)->mbase + 0x20970 + (i) * 0x4000 + (j) * 4)
|
||||
#define I10NM_GET_MCMTR(m, i) \
|
||||
readl((m)->mbase + 0x20ef8 + (i) * 0x4000)
|
||||
|
||||
#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
|
||||
#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
|
||||
@ -148,7 +151,7 @@ static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
|
||||
{
|
||||
u32 mcmtr;
|
||||
|
||||
mcmtr = *(u32 *)(imc->mbase + 0x20ef8 + chan * 0x4000);
|
||||
mcmtr = I10NM_GET_MCMTR(imc, chan);
|
||||
edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
|
||||
|
||||
return !!GET_BITFIELD(mcmtr, 2, 2);
|
||||
|
Loading…
Reference in New Issue
Block a user