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mlxsw: cmd: Add cmd_mbox.query_fw.cff_support

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PGT, a port-group table is an in-HW block of specialized memory that holds
sets of ports. Allocated within the PGT are series of flood tables that
describe to which ports traffic of various types (unknown UC, BC, MC)
should be flooded from which FID. The hitherto-used layout of these flood
tables is being replaced with a more flexible scheme, called compressed FID
flooding (CFF). CFF can be configured through CONFIG_PROFILE.flood_mode.

cff_support determines whether CONFIG_PROFILE.flood_mode can be set to CFF.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/af727d0e1095e30fa45c7e60404637cdc491aeec.1700503643.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Petr Machata 2023-11-20 19:25:18 +01:00 committed by Jakub Kicinski
parent dd891b5b10
commit 8405d66262
1 changed files with 6 additions and 0 deletions
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6
drivers/net/ethernet/mellanox/mlxsw/cmd.h
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@ -282,6 +282,12 @@ MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
*/
MLXSW_ITEM32(cmd_mbox, query_fw, lag_mode_support, 0x18, 1, 1);
/* cmd_mbox_query_fw_cff_support
* 0: CONFIG_PROFILE.flood_mode = 5 (CFF) is not supported by FW
* 1: CONFIG_PROFILE.flood_mode = 5 (CFF) is supported by FW
*/
MLXSW_ITEM32(cmd_mbox, query_fw, cff_support, 0x18, 2, 1);
/* cmd_mbox_query_fw_clr_int_base_offset
* Clear Interrupt register's offset from clr_int_bar register
* in PCI address space.