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arm64: dts: imx8m: Fix the SPI chipselect polarity

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The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:

[    4.854337] m25p80@0 enforce active low on chipselect handle

Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.

The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:

 * SPI children have active low chip selects
 * by default. This can be specified negatively
 * by just omitting "spi-cs-high" in the
 * device node, or actively by tagging on
 * GPIO_ACTIVE_LOW as flag in the device
 * tree. If the line is simultaneously
 * tagged as active low in the device tree
 * and has the "spi-cs-high" set, we get a
 * conflict and the "spi-cs-high" flag will
 * take precedence.

To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam 2020-08-19 19:02:19 -03:00 committed by Shawn Guo
parent bcf7206fe9
commit 843b993c2d
2 changed files with 2 additions and 2 deletions
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2
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@ -70,7 +70,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
cs-gpios = <&gpio5 9 0>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
eeprom@0 {

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
View File

@ -15,7 +15,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;