Merge branch 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 AMD northbridge updates from Ingo Molnar:
"Update DF/SMN access and k10temp for AMD F17h M30h, by Brian Woods:
'Updates the data fabric/system management network code needed to get
k10temp working for M30h. Since there are now processors which have
multiple roots per DF/SMN interface, there needs to some logic which
skips N-1 root complexes per DF/SMN interface. This is because the
root complexes per interface are redundant (as far as DF/SMN goes).
These changes shouldn't effect past processors and, for F17h M0Xh,
the mappings stay the same.'
The hwmon changes were seen and acked by hwmon maintainer Guenter Roeck"
* 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
hwmon/k10temp: Add support for AMD family 17h, model 30h CPUs
x86/amd_nb: Add PCI device IDs for family 17h, model 30h
x86/amd_nb: Add support for newer PCI topologies
hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs
This commit is contained in:
Linus Torvalds
commit
8465625ab4
@ -11,14 +11,15 @@
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/spinlock.h>
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
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#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
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#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
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/* Protect the PCI config register pairs used for SMN and DF indirect access. */
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static DEFINE_MUTEX(smn_mutex);
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@ -28,9 +29,11 @@ static u32 *flush_words;
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static const struct pci_device_id amd_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
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{}
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};
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#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
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const struct pci_device_id amd_nb_misc_ids[] = {
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@ -44,6 +47,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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{}
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};
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@ -57,6 +61,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
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{}
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};
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@ -214,7 +219,10 @@ int amd_cache_northbridges(void)
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const struct pci_device_id *root_ids = amd_root_ids;
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struct pci_dev *root, *misc, *link;
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struct amd_northbridge *nb;
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u16 i = 0;
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u16 roots_per_misc = 0;
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u16 misc_count = 0;
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u16 root_count = 0;
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u16 i, j;
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if (amd_northbridges.num)
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return 0;
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@ -227,26 +235,55 @@ int amd_cache_northbridges(void)
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misc = NULL;
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while ((misc = next_northbridge(misc, misc_ids)) != NULL)
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i++;
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misc_count++;
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if (!i)
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if (!misc_count)
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return -ENODEV;
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nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
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root = NULL;
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while ((root = next_northbridge(root, root_ids)) != NULL)
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root_count++;
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if (root_count) {
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roots_per_misc = root_count / misc_count;
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/*
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* There should be _exactly_ N roots for each DF/SMN
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* interface.
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*/
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if (!roots_per_misc || (root_count % roots_per_misc)) {
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pr_info("Unsupported AMD DF/PCI configuration found\n");
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return -ENODEV;
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}
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}
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nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
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if (!nb)
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return -ENOMEM;
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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amd_northbridges.num = misc_count;
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link = misc = root = NULL;
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for (i = 0; i != amd_northbridges.num; i++) {
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for (i = 0; i < amd_northbridges.num; i++) {
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node_to_amd_nb(i)->root = root =
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next_northbridge(root, root_ids);
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, link_ids);
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/*
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* If there are more PCI root devices than data fabric/
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* system management network interfaces, then the (N)
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* PCI roots per DF/SMN interface are functionally the
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* same (for DF/SMN access) and N-1 are redundant. N-1
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* PCI roots should be skipped per DF/SMN interface so
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* the following DF/SMN interfaces get mapped to
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* correct PCI roots.
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*/
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for (j = 1; j < roots_per_misc; j++)
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root = next_northbridge(root, root_ids);
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}
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if (amd_gart_present())
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@ -23,6 +23,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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#include <asm/processor.h>
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@ -41,14 +42,6 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
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#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#endif
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/* CPUID function 0x80000001, ebx */
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#define CPUID_PKGTYPE_MASK 0xf0000000
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#define CPUID_PKGTYPE_F 0x00000000
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@ -367,6 +360,7 @@ static const struct pci_device_id k10temp_id_table[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, k10temp_id_table);
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@ -545,6 +545,9 @@
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#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
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#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
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