iio: dac: ad7293: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 0bb12606c05f ("iio:dac:ad7293: add support for AD7293") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-57-jic23@kernel.org
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@ -144,7 +144,7 @@ struct ad7293_state {
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struct regulator *reg_avdd;
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struct regulator *reg_vdrive;
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u8 page_select;
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u8 data[3] ____cacheline_aligned;
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u8 data[3] __aligned(IIO_DMA_MINALIGN);
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};
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static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
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