- Add gxl internal dac gate clock id
- Add g12a SPICC SCLK Source clock IDs -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAl5vr78ACgkQd9zb2sjI SdHZiw//V+FaGx+Y3kd1nost/vguCjyZMA4VuGwaqhiMKNDEbk1wVHIz8MtGZS4T rsb+4800mkvaux/kPLXeZinKSNaUZON5GRwpCH3qyCS3nIoaXrfm0bhGEaYA3KxI 0eCLRd4jb4RInKCELXhq01OkOX8/hcISXDyqarbt9jiGU6J7KnyV38CqrH3wVtgy F+SU9ckBaUIZ3WJ6OZAVzs7Sqj6xvv94rEWN7EmDsz6zflHmdU3iSHfC/VpenJou xxzM1PtVEEPME44+I/Eao0qHk2A6YbgubE7+OqXfgyLqiDSWLI//rV6ZzfqJ7Nju dJFVqL8AkMKgY2is+Jwle0a6M7y1QgqJnhj9WJGg02QYbjUztFYcgGANaB/Op/aU qsmKc4QXJRrd+ydqCUyEpZNl+o+ZTBvC/+qpgzWAy01KUYBZ/t62/Ylb3sYMOiLJ SJFbJoJs86L0WrdAPwzhpA58+L5jenViRiqacwI4kc42mo3CnG0UW3pMmDDysGCv +zZ9c0sZ0PoyBL2A7NRzWtyjET64F8xYklohOFLoZ0PFz721hApGs7i6OSgPRsZj 3XPFfv+In+H02el+8F8z9BwGFtBGnJA/9+zxpEx9zLWPkULh6lRsg4LjD2eKmxCc 8nmwBCrDdUUxtRxBQDv8VjMANv3u0Stt3b5JuyLJ5i+TzOeyS5U= =jTVs -----END PGP SIGNATURE----- Merge tag 'clk-meson-dt-v5.7-1' of git://github.com/BayLibre/clk-meson into v5.7/dt64 - Add gxl internal dac gate clock id - Add g12a SPICC SCLK Source clock IDs * tag 'clk-meson-dt-v5.7-1' of git://github.com/BayLibre/clk-meson: dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs dt-bindings: clk: meson: add the gxl internal dac gate
This commit is contained in:
commit
84b4cea705
@ -143,5 +143,7 @@
|
||||
#define CLKID_CPU1_CLK 253
|
||||
#define CLKID_CPU2_CLK 254
|
||||
#define CLKID_CPU3_CLK 255
|
||||
#define CLKID_SPICC0_SCLK 258
|
||||
#define CLKID_SPICC1_SCLK 261
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
@ -146,5 +146,6 @@
|
||||
#define CLKID_CTS_VDAC 201
|
||||
#define CLKID_HDMI_TX 202
|
||||
#define CLKID_HDMI 205
|
||||
#define CLKID_ACODEC 206
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
Loading…
x
Reference in New Issue
Block a user