mailbox: cmdq: add mt8192 support
add mt8192 support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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@ -36,6 +36,8 @@
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#define CMDQ_THR_WAIT_TOKEN 0x30
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#define CMDQ_THR_PRIORITY 0x40
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#define GCE_GCTL_VALUE 0x48
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#define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
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#define CMDQ_THR_ENABLED 0x1
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#define CMDQ_THR_DISABLED 0x0
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@ -76,11 +78,13 @@ struct cmdq {
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struct clk *clock;
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bool suspended;
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u8 shift_pa;
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bool control_by_sw;
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};
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struct gce_plat {
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u32 thread_nr;
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u8 shift;
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bool control_by_sw;
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};
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u8 cmdq_get_shift_pa(struct mbox_chan *chan)
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@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq)
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int i;
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WARN_ON(clk_enable(cmdq->clock) < 0);
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if (cmdq->control_by_sw)
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writel(0x7, cmdq->base + GCE_GCTL_VALUE);
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writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
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for (i = 0; i <= CMDQ_MAX_EVENT; i++)
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writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
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@ -540,6 +546,7 @@ static int cmdq_probe(struct platform_device *pdev)
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cmdq->thread_nr = plat_data->thread_nr;
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cmdq->shift_pa = plat_data->shift;
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cmdq->control_by_sw = plat_data->control_by_sw;
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cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
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err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
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"mtk_cmdq", cmdq);
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@ -605,11 +612,14 @@ static const struct dev_pm_ops cmdq_pm_ops = {
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static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
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static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
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static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
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static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3,
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.control_by_sw = true};
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static const struct of_device_id cmdq_of_ids[] = {
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{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
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{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
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{.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
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{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
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{}
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};
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