x86/oprofile: add CONFIG_OPROFILE_IBS option
Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: oprofile-list <oprofile-list@lists.sourceforge.net> Cc: Robert Richter <robert.richter@amd.com> Cc: Barry Kasindorf <barry.kasindorf@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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arch/Kconfig
14
arch/Kconfig
@ -13,6 +13,20 @@ config OPROFILE
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If unsure, say N.
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If unsure, say N.
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config OPROFILE_IBS
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bool "OProfile AMD IBS support (EXPERIMENTAL)"
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default n
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depends on OPROFILE && SMP && X86
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help
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Instruction-Based Sampling (IBS) is a new profiling
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technique that provides rich, precise program performance
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information. IBS is introduced by AMD Family10h processors
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(AMD Opteron Quad-Core processor “Barcelona”) to overcome
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the limitations of conventional performance counter
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sampling.
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If unsure, say N.
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config HAVE_OPROFILE
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config HAVE_OPROFILE
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def_bool n
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def_bool n
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@ -47,6 +47,10 @@
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#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
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#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
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#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
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#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
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static unsigned long reset_value[NUM_COUNTERS];
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#ifdef CONFIG_OPROFILE_IBS
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/* IbsFetchCtl bits/masks */
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
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#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
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#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
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#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
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@ -104,7 +108,6 @@ struct ibs_op_sample {
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*/
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*/
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static void clear_ibs_nmi(void);
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static void clear_ibs_nmi(void);
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static unsigned long reset_value[NUM_COUNTERS];
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static int ibs_allowed; /* AMD Family10h and later */
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static int ibs_allowed; /* AMD Family10h and later */
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struct op_ibs_config {
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struct op_ibs_config {
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@ -118,6 +121,8 @@ struct op_ibs_config {
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static struct op_ibs_config ibs_config;
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static struct op_ibs_config ibs_config;
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#endif
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/* functions for op_amd_spec */
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/* functions for op_amd_spec */
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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@ -188,6 +193,8 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
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}
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}
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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static inline int
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static inline int
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op_amd_handle_ibs(struct pt_regs * const regs,
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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struct op_msrs const * const msrs)
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@ -261,6 +268,8 @@ op_amd_handle_ibs(struct pt_regs * const regs,
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return 1;
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return 1;
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}
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}
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#endif
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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struct op_msrs const * const msrs)
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{
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{
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@ -277,7 +286,9 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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}
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}
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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op_amd_handle_ibs(regs, msrs);
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op_amd_handle_ibs(regs, msrs);
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#endif
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/* See op_model_ppro.c */
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/* See op_model_ppro.c */
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return 1;
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return 1;
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@ -294,6 +305,8 @@ static void op_amd_start(struct op_msrs const * const msrs)
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CTRL_WRITE(low, high, msrs, i);
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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if (ibs_allowed && ibs_config.fetch_enabled) {
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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high = IBS_FETCH_HIGH_ENABLE;
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high = IBS_FETCH_HIGH_ENABLE;
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@ -305,6 +318,7 @@ static void op_amd_start(struct op_msrs const * const msrs)
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high = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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#endif
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}
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}
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@ -323,6 +337,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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CTRL_WRITE(low, high, msrs, i);
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CTRL_WRITE(low, high, msrs, i);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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if (ibs_allowed && ibs_config.fetch_enabled) {
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if (ibs_allowed && ibs_config.fetch_enabled) {
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low = 0; /* clear max count and enable */
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low = 0; /* clear max count and enable */
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high = 0;
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high = 0;
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@ -334,6 +349,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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high = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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#endif
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}
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}
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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@ -350,17 +366,10 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
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}
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}
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}
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}
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#ifndef CONFIG_SMP
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#ifndef CONFIG_OPROFILE_IBS
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/* no IBS support */
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/* no IBS support */
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static void setup_ibs(void)
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{
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ibs_allowed = 0;
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}
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static void clear_ibs_nmi(void) {}
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static int op_amd_init(struct oprofile_operations *ops)
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static int op_amd_init(struct oprofile_operations *ops)
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{
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{
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return 0;
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return 0;
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@ -441,8 +450,12 @@ static void setup_ibs(void)
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if (!ibs_allowed)
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if (!ibs_allowed)
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return;
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return;
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if (pfm_amd64_setup_eilvt())
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if (pfm_amd64_setup_eilvt()) {
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ibs_allowed = 0;
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ibs_allowed = 0;
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return;
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}
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printk(KERN_INFO "oprofile: AMD IBS detected\n");
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}
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}
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@ -328,6 +328,8 @@ static void add_trace_begin(void)
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add_event_entry(TRACE_BEGIN_CODE);
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add_event_entry(TRACE_BEGIN_CODE);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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#define IBS_FETCH_CODE_SIZE 2
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#define IBS_FETCH_CODE_SIZE 2
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#define IBS_OP_CODE_SIZE 5
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#define IBS_OP_CODE_SIZE 5
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#define IBS_EIP(offset) \
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#define IBS_EIP(offset) \
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@ -390,6 +392,8 @@ static void add_ibs_begin(struct oprofile_cpu_buffer *cpu_buf, int code,
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}
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}
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}
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}
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#endif
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static void add_sample_entry(unsigned long offset, unsigned long event)
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static void add_sample_entry(unsigned long offset, unsigned long event)
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{
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{
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add_event_entry(offset);
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add_event_entry(offset);
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@ -586,6 +590,7 @@ void sync_buffer(int cpu)
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} else if (s->event == CPU_TRACE_BEGIN) {
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} else if (s->event == CPU_TRACE_BEGIN) {
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state = sb_bt_start;
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state = sb_bt_start;
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add_trace_begin();
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add_trace_begin();
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#ifdef CONFIG_OPROFILE_IBS
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} else if (s->event == IBS_FETCH_BEGIN) {
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} else if (s->event == IBS_FETCH_BEGIN) {
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state = sb_bt_start;
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state = sb_bt_start;
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add_ibs_begin(cpu_buf,
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add_ibs_begin(cpu_buf,
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@ -594,6 +599,7 @@ void sync_buffer(int cpu)
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state = sb_bt_start;
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state = sb_bt_start;
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add_ibs_begin(cpu_buf,
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add_ibs_begin(cpu_buf,
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IBS_OP_CODE, in_kernel, mm);
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IBS_OP_CODE, in_kernel, mm);
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#endif
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} else {
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} else {
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struct mm_struct *oldmm = mm;
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struct mm_struct *oldmm = mm;
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@ -253,6 +253,8 @@ void oprofile_add_sample(struct pt_regs * const regs, unsigned long event)
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oprofile_add_ext_sample(pc, regs, event, is_kernel);
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oprofile_add_ext_sample(pc, regs, event, is_kernel);
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}
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}
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#ifdef CONFIG_OPROFILE_IBS
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#define MAX_IBS_SAMPLE_SIZE 14
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#define MAX_IBS_SAMPLE_SIZE 14
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static int log_ibs_sample(struct oprofile_cpu_buffer *cpu_buf,
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static int log_ibs_sample(struct oprofile_cpu_buffer *cpu_buf,
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unsigned long pc, int is_kernel, unsigned int *ibs, int ibs_code)
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unsigned long pc, int is_kernel, unsigned int *ibs, int ibs_code)
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@ -318,6 +320,8 @@ void oprofile_add_ibs_sample(struct pt_regs *const regs,
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oprofile_ops.backtrace(regs, backtrace_depth);
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oprofile_ops.backtrace(regs, backtrace_depth);
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}
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}
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#endif
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void oprofile_add_pc(unsigned long pc, int is_kernel, unsigned long event)
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void oprofile_add_pc(unsigned long pc, int is_kernel, unsigned long event)
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{
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{
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struct oprofile_cpu_buffer *cpu_buf = &__get_cpu_var(cpu_buffer);
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struct oprofile_cpu_buffer *cpu_buf = &__get_cpu_var(cpu_buffer);
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