staging: m57621-mmc: delete driver from the tree.
[ Upstream commit 441bf7332d55c4d34afae9ffc3bbec621093f4d1 ] The license text in this driver is "interesting" and not really obvious that it is supposed to be able to be distributed in the kernel source tree. Yes, the MODULE_LICENSE() text says GPL, so it's probably ok, but to be safe, I am deleting this driver. I will be glad to add it back if the license is properly sorted out, but for now, this isn't worth the potential risk, I should have never taken it in the first place. Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: NeilBrown <neil@brown.name> Cc: George Hilliard <thirtythreeforty@gmail.com> Cc: "Christian Lütke-Stetzkamp" <christian@lkamp.de> Cc: Nishad Kamdar <nishadkamdar@gmail.com> Cc: Sergej Perschin <ser.perschin@gmail.com> Cc: John Crispin <blogic@openwrt.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Greg Kroah-Hartman
parent
8872a0d949
commit
854e8c240f
@ -114,8 +114,6 @@ source "drivers/staging/mt7621-spi/Kconfig"
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source "drivers/staging/mt7621-dma/Kconfig"
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source "drivers/staging/mt7621-mmc/Kconfig"
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source "drivers/staging/mt7621-eth/Kconfig"
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source "drivers/staging/mt7621-dts/Kconfig"
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@ -47,7 +47,6 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-pci/
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obj-$(CONFIG_SOC_MT7621) += mt7621-pinctrl/
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obj-$(CONFIG_SOC_MT7621) += mt7621-spi/
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obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
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obj-$(CONFIG_SOC_MT7621) += mt7621-mmc/
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obj-$(CONFIG_SOC_MT7621) += mt7621-eth/
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obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
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obj-$(CONFIG_STAGING_GASKET_FRAMEWORK) += gasket/
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@ -1,16 +0,0 @@
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config MTK_MMC
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tristate "MTK SD/MMC"
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depends on !MTD_NAND_RALINK && MMC
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config MTK_AEE_KDUMP
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bool "MTK AEE KDUMP"
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depends on MTK_MMC
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config MTK_MMC_CD_POLL
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bool "Card Detect with Polling"
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depends on MTK_MMC
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config MTK_MMC_EMMC_8BIT
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bool "eMMC 8-bit support"
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depends on MTK_MMC && RALINK_MT7628
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@ -1,42 +0,0 @@
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# Copyright Statement:
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#
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# This software/firmware and related documentation ("MediaTek Software") are
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# protected under relevant copyright laws. The information contained herein
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# is confidential and proprietary to MediaTek Inc. and/or its licensors.
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# Without the prior written permission of MediaTek inc. and/or its licensors,
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# any reproduction, modification, use or disclosure of MediaTek Software,
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# and information contained herein, in whole or in part, shall be strictly prohibited.
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#
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# MediaTek Inc. (C) 2010. All rights reserved.
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#
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# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
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# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
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# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
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# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
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# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
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# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
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# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
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# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
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# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
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# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
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# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
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# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
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# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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#
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# The following software/firmware and/or related documentation ("MediaTek Software")
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# have been modified by MediaTek Inc. All revisions are subject to any receiver's
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# applicable license agreements with MediaTek Inc.
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obj-$(CONFIG_MTK_MMC) += mtk_sd.o
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mtk_sd-objs := sd.o dbg.o
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ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
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EXTRA_CFLAGS += -DMT6575_SD_DEBUG
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endif
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clean:
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@rm -f *.o modules.order .*.cmd
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@ -1,8 +0,0 @@
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- general code review and clean up
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- ensure device-tree requirements are documented
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- should probably be merged with drivers/mmc/host/mtk-sd.c
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- possibly fix to work with highmem pages so a bounce buffer isn't
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needed.
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Cc: NeilBrown <neil@brown.name>
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@ -1,63 +0,0 @@
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/* Copyright Statement:
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*
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* This software/firmware and related documentation ("MediaTek Software") are
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* protected under relevant copyright laws. The information contained herein
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* is confidential and proprietary to MediaTek Inc. and/or its licensors.
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* Without the prior written permission of MediaTek inc. and/or its licensors,
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* any reproduction, modification, use or disclosure of MediaTek Software,
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* and information contained herein, in whole or in part, shall be strictly prohibited.
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*/
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/* MediaTek Inc. (C) 2010. All rights reserved.
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*
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* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
|
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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
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* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
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* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
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* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
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* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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*
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* The following software/firmware and/or related documentation ("MediaTek Software")
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* have been modified by MediaTek Inc. All revisions are subject to any receiver's
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* applicable license agreements with MediaTek Inc.
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*/
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#ifndef __ARCH_ARM_MACH_BOARD_H
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#define __ARCH_ARM_MACH_BOARD_H
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#define MSDC_CD_PIN_EN BIT(0) /* card detection pin is wired */
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#define MSDC_WP_PIN_EN BIT(1) /* write protection pin is wired */
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#define MSDC_RST_PIN_EN BIT(2) /* emmc reset pin is wired */
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#define MSDC_REMOVABLE BIT(5) /* removable slot */
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#define MSDC_SMPL_RISING (0)
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#define MSDC_SMPL_FALLING (1)
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#define MSDC_CMD_PIN (0)
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#define MSDC_DAT_PIN (1)
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#define MSDC_CD_PIN (2)
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#define MSDC_WP_PIN (3)
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#define MSDC_RST_PIN (4)
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struct msdc_hw {
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unsigned char clk_src; /* host clock source */
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unsigned long flags; /* hardware capability flags */
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/* config gpio pull mode */
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void (*config_gpio_pin)(int type, int pull);
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};
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extern struct msdc_hw msdc0_hw;
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#endif /* __ARCH_ARM_MACH_BOARD_H */
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@ -1,307 +0,0 @@
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/* Copyright Statement:
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*
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* This software/firmware and related documentation ("MediaTek Software") are
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* protected under relevant copyright laws. The information contained herein
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* is confidential and proprietary to MediaTek Inc. and/or its licensors.
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* Without the prior written permission of MediaTek inc. and/or its licensors,
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* any reproduction, modification, use or disclosure of MediaTek Software,
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* and information contained herein, in whole or in part, shall be strictly prohibited.
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*
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* MediaTek Inc. (C) 2010. All rights reserved.
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*
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* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
|
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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
|
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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
|
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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
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* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
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* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
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* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
|
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* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
|
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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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*
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* The following software/firmware and/or related documentation ("MediaTek Software")
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* have been modified by MediaTek Inc. All revisions are subject to any receiver's
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* applicable license agreements with MediaTek Inc.
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*/
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#include <linux/version.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/kthread.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/proc_fs.h>
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#include <linux/string.h>
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#include <linux/uaccess.h>
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// #include <mach/mt6575_gpt.h> /* --- by chhung */
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#include "dbg.h"
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#include "mt6575_sd.h"
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#include <linux/seq_file.h>
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static char cmd_buf[256];
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/* for debug zone */
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unsigned int sd_debug_zone[4] = {
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0,
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0,
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0,
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0
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};
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#if defined(MT6575_SD_DEBUG)
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/* for driver profile */
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#define TICKS_ONE_MS (13000)
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u32 gpt_enable;
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u32 sdio_pro_enable; /* make sure gpt is enabled */
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u32 sdio_pro_time; /* no more than 30s */
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struct sdio_profile sdio_perfomance = {0};
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#if 0 /* --- chhung */
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void msdc_init_gpt(void)
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{
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GPT_CONFIG config;
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config.num = GPT6;
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config.mode = GPT_FREE_RUN;
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config.clkSrc = GPT_CLK_SRC_SYS;
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config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
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if (GPT_Config(config) == FALSE)
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return;
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GPT_Start(GPT6);
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}
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#endif /* end of --- */
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u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
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{
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u32 ret = 0;
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if (new_H32 == old_H32) {
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ret = new_L32 - old_L32;
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} else if (new_H32 == (old_H32 + 1)) {
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if (new_L32 > old_L32)
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pr_debug("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
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ret = (0xffffffff - old_L32);
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ret += new_L32;
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} else {
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pr_debug("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
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}
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return ret;
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}
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void msdc_sdio_profile(struct sdio_profile *result)
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{
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struct cmd_profile *cmd;
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u32 i;
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pr_debug("sdio === performance dump ===\n");
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pr_debug("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
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result->total_tc, result->total_tc / TICKS_ONE_MS,
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result->total_tx_bytes, result->total_rx_bytes);
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/* CMD52 Dump */
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cmd = &result->cmd52_rx;
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pr_debug("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
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cmd = &result->cmd52_tx;
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pr_debug("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
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/* CMD53 Rx bytes + block mode */
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for (i = 0; i < 512; i++) {
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cmd = &result->cmd53_rx_byte[i];
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if (cmd->count) {
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pr_debug("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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for (i = 0; i < 100; i++) {
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cmd = &result->cmd53_rx_blk[i];
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if (cmd->count) {
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pr_debug("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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/* CMD53 Tx bytes + block mode */
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for (i = 0; i < 512; i++) {
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cmd = &result->cmd53_tx_byte[i];
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if (cmd->count) {
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pr_debug("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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for (i = 0; i < 100; i++) {
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cmd = &result->cmd53_tx_blk[i];
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if (cmd->count) {
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pr_debug("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
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cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
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cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
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}
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}
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pr_debug("sdio === performance dump done ===\n");
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}
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//========= sdio command table ===========
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void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
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{
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struct sdio_profile *result = &sdio_perfomance;
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struct cmd_profile *cmd;
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u32 block;
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if (sdio_pro_enable == 0)
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return;
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if (opcode == 52) {
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cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
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} else if (opcode == 53) {
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if (sizes < 512) {
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cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
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} else {
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block = sizes / 512;
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if (block >= 99) {
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pr_err("cmd53 error blocks\n");
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while (1)
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;
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}
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cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
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}
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} else {
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return;
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}
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/* update the members */
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if (ticks > cmd->max_tc)
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cmd->max_tc = ticks;
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if (cmd->min_tc == 0 || ticks < cmd->min_tc)
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cmd->min_tc = ticks;
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cmd->tot_tc += ticks;
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cmd->tot_bytes += sizes;
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cmd->count++;
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if (bRx)
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result->total_rx_bytes += sizes;
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else
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result->total_tx_bytes += sizes;
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result->total_tc += ticks;
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/* dump when total_tc > 30s */
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if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
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msdc_sdio_profile(result);
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memset(result, 0, sizeof(struct sdio_profile));
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}
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}
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//========== driver proc interface ===========
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static int msdc_debug_proc_read(struct seq_file *s, void *p)
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{
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seq_puts(s, "\n=========================================\n");
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seq_puts(s, "Index<0> + Id + Zone\n");
|
||||
seq_puts(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
|
||||
seq_puts(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
|
||||
seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
|
||||
seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
|
||||
seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
|
||||
seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
|
||||
|
||||
seq_puts(s, "Index<3> + SDIO_PROFILE + TIME\n");
|
||||
seq_puts(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
|
||||
seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
|
||||
seq_puts(s, "=========================================\n\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t msdc_debug_proc_write(struct file *file,
|
||||
const char __user *buf,
|
||||
size_t count, loff_t *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
int cmd, p1, p2;
|
||||
int id, zone;
|
||||
int mode, size;
|
||||
|
||||
if (count == 0)
|
||||
return -1;
|
||||
if (count > 255)
|
||||
count = 255;
|
||||
|
||||
if (copy_from_user(cmd_buf, buf, count))
|
||||
return -EFAULT;
|
||||
|
||||
cmd_buf[count] = '\0';
|
||||
pr_debug("msdc Write %s\n", cmd_buf);
|
||||
|
||||
sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
|
||||
|
||||
if (cmd == SD_TOOL_ZONE) {
|
||||
id = p1;
|
||||
zone = p2;
|
||||
zone &= 0x3ff;
|
||||
pr_debug("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
|
||||
if (id >= 0 && id <= 3) {
|
||||
sd_debug_zone[id] = zone;
|
||||
} else if (id == 4) {
|
||||
sd_debug_zone[0] = sd_debug_zone[1] = zone;
|
||||
sd_debug_zone[2] = sd_debug_zone[3] = zone;
|
||||
} else {
|
||||
pr_err("msdc host_id error when set debug zone\n");
|
||||
}
|
||||
} else if (cmd == SD_TOOL_SDIO_PROFILE) {
|
||||
if (p1 == 1) { /* enable profile */
|
||||
if (gpt_enable == 0) {
|
||||
// msdc_init_gpt(); /* --- by chhung */
|
||||
gpt_enable = 1;
|
||||
}
|
||||
sdio_pro_enable = 1;
|
||||
if (p2 == 0)
|
||||
p2 = 1;
|
||||
if (p2 >= 30)
|
||||
p2 = 30;
|
||||
sdio_pro_time = p2;
|
||||
} else if (p1 == 0) {
|
||||
/* todo */
|
||||
sdio_pro_enable = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static int msdc_debug_show(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, msdc_debug_proc_read, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations msdc_debug_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = msdc_debug_show,
|
||||
.read = seq_read,
|
||||
.write = msdc_debug_proc_write,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
void msdc_debug_proc_init(void)
|
||||
{
|
||||
proc_create("msdc_debug", 0660, NULL, &msdc_debug_fops);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
|
||||
#endif
|
||||
@ -1,149 +0,0 @@
|
||||
/* Copyright Statement:
|
||||
*
|
||||
* This software/firmware and related documentation ("MediaTek Software") are
|
||||
* protected under relevant copyright laws. The information contained herein
|
||||
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
|
||||
* Without the prior written permission of MediaTek inc. and/or its licensors,
|
||||
* any reproduction, modification, use or disclosure of MediaTek Software,
|
||||
* and information contained herein, in whole or in part, shall be strictly prohibited.
|
||||
*
|
||||
* MediaTek Inc. (C) 2010. All rights reserved.
|
||||
*
|
||||
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
|
||||
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
|
||||
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
|
||||
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
|
||||
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
|
||||
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
|
||||
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
|
||||
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
|
||||
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
|
||||
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
|
||||
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
|
||||
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
|
||||
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
|
||||
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
|
||||
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
|
||||
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
|
||||
*
|
||||
* The following software/firmware and/or related documentation ("MediaTek Software")
|
||||
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
|
||||
* applicable license agreements with MediaTek Inc.
|
||||
*/
|
||||
#ifndef __MT_MSDC_DEUBG__
|
||||
#define __MT_MSDC_DEUBG__
|
||||
|
||||
//==========================
|
||||
extern u32 sdio_pro_enable;
|
||||
/* for a type command, e.g. CMD53, 2 blocks */
|
||||
struct cmd_profile {
|
||||
u32 max_tc; /* Max tick count */
|
||||
u32 min_tc;
|
||||
u32 tot_tc; /* total tick count */
|
||||
u32 tot_bytes;
|
||||
u32 count; /* the counts of the command */
|
||||
};
|
||||
|
||||
/* dump when total_tc and total_bytes */
|
||||
struct sdio_profile {
|
||||
u32 total_tc; /* total tick count of CMD52 and CMD53 */
|
||||
u32 total_tx_bytes; /* total bytes of CMD53 Tx */
|
||||
u32 total_rx_bytes; /* total bytes of CMD53 Rx */
|
||||
|
||||
/*CMD52*/
|
||||
struct cmd_profile cmd52_tx;
|
||||
struct cmd_profile cmd52_rx;
|
||||
|
||||
/*CMD53 in byte unit */
|
||||
struct cmd_profile cmd53_tx_byte[512];
|
||||
struct cmd_profile cmd53_rx_byte[512];
|
||||
|
||||
/*CMD53 in block unit */
|
||||
struct cmd_profile cmd53_tx_blk[100];
|
||||
struct cmd_profile cmd53_rx_blk[100];
|
||||
};
|
||||
|
||||
//==========================
|
||||
enum msdc_dbg {
|
||||
SD_TOOL_ZONE = 0,
|
||||
SD_TOOL_DMA_SIZE = 1,
|
||||
SD_TOOL_PM_ENABLE = 2,
|
||||
SD_TOOL_SDIO_PROFILE = 3,
|
||||
};
|
||||
|
||||
/* Debug message event */
|
||||
#define DBG_EVT_NONE (0) /* No event */
|
||||
#define DBG_EVT_DMA (1 << 0) /* DMA related event */
|
||||
#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
|
||||
#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
|
||||
#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
|
||||
#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
|
||||
#define DBG_EVT_FUC (1 << 5) /* Function event */
|
||||
#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
|
||||
#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
|
||||
#define DBG_EVT_WRN (1 << 8) /* Warning event */
|
||||
#define DBG_EVT_PWR (1 << 9) /* Power event */
|
||||
#define DBG_EVT_ALL (0xffffffff)
|
||||
|
||||
#define DBG_EVT_MASK (DBG_EVT_ALL)
|
||||
|
||||
extern unsigned int sd_debug_zone[4];
|
||||
#define TAG "msdc"
|
||||
#if 0 /* +++ chhung */
|
||||
#define BUG_ON(x) \
|
||||
do { \
|
||||
if (x) { \
|
||||
printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
|
||||
while (1) \
|
||||
; \
|
||||
} \
|
||||
} while (0)
|
||||
#endif /* end of +++ */
|
||||
|
||||
#define N_MSG(evt, fmt, args...)
|
||||
/*
|
||||
do { \
|
||||
if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
|
||||
host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} \
|
||||
} while(0)
|
||||
*/
|
||||
|
||||
#define ERR_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
|
||||
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while (0);
|
||||
|
||||
#if 1
|
||||
//defined CONFIG_MTK_MMC_CD_POLL
|
||||
#define INIT_MSG(fmt, args...)
|
||||
#define IRQ_MSG(fmt, args...)
|
||||
#else
|
||||
#define INIT_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
|
||||
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
|
||||
} while (0);
|
||||
|
||||
/* PID in ISR in not corrent */
|
||||
#define IRQ_MSG(fmt, args...) \
|
||||
do { \
|
||||
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
|
||||
host->id, ##args, __FUNCTION__, __LINE__); \
|
||||
} while (0);
|
||||
#endif
|
||||
|
||||
void msdc_debug_proc_init(void);
|
||||
|
||||
#if 0 /* --- chhung */
|
||||
void msdc_init_gpt(void);
|
||||
extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
|
||||
#endif /* end of --- */
|
||||
u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
|
||||
void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
|
||||
|
||||
#endif
|
||||
@ -1,488 +0,0 @@
|
||||
/* Copyright Statement:
|
||||
*
|
||||
* This software/firmware and related documentation ("MediaTek Software") are
|
||||
* protected under relevant copyright laws. The information contained herein
|
||||
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
|
||||
* Without the prior written permission of MediaTek inc. and/or its licensors,
|
||||
* any reproduction, modification, use or disclosure of MediaTek Software,
|
||||
* and information contained herein, in whole or in part, shall be strictly prohibited.
|
||||
*/
|
||||
/* MediaTek Inc. (C) 2010. All rights reserved.
|
||||
*
|
||||
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
|
||||
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
|
||||
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
|
||||
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
|
||||
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
|
||||
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
|
||||
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
|
||||
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
|
||||
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
|
||||
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
|
||||
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
|
||||
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
|
||||
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
|
||||
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
|
||||
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
|
||||
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
|
||||
*
|
||||
* The following software/firmware and/or related documentation ("MediaTek Software")
|
||||
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
|
||||
* applicable license agreements with MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef MT6575_SD_H
|
||||
#define MT6575_SD_H
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
// #include <mach/mt6575_reg_base.h> /* --- by chhung */
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Common Definition */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#define MSDC_FIFO_SZ (128)
|
||||
#define MSDC_FIFO_THD (64) // (128)
|
||||
#define MSDC_NUM (4)
|
||||
|
||||
#define MSDC_MS (0)
|
||||
#define MSDC_SDMMC (1)
|
||||
|
||||
#define MSDC_BUS_1BITS (0)
|
||||
#define MSDC_BUS_4BITS (1)
|
||||
#define MSDC_BUS_8BITS (2)
|
||||
|
||||
#define MSDC_BRUST_8B (3)
|
||||
#define MSDC_BRUST_16B (4)
|
||||
#define MSDC_BRUST_32B (5)
|
||||
#define MSDC_BRUST_64B (6)
|
||||
|
||||
#define MSDC_PIN_PULL_NONE (0)
|
||||
#define MSDC_PIN_PULL_DOWN (1)
|
||||
#define MSDC_PIN_PULL_UP (2)
|
||||
#define MSDC_PIN_KEEP (3)
|
||||
|
||||
#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
|
||||
#define MSDC_MIN_SCLK (260000)
|
||||
|
||||
#define MSDC_AUTOCMD12 (0x0001)
|
||||
#define MSDC_AUTOCMD23 (0x0002)
|
||||
#define MSDC_AUTOCMD19 (0x0003)
|
||||
|
||||
#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
|
||||
#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
|
||||
|
||||
enum {
|
||||
RESP_NONE = 0,
|
||||
RESP_R1,
|
||||
RESP_R2,
|
||||
RESP_R3,
|
||||
RESP_R4,
|
||||
RESP_R5,
|
||||
RESP_R6,
|
||||
RESP_R7,
|
||||
RESP_R1B
|
||||
};
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Register Offset */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
#define MSDC_CFG (0x0)
|
||||
#define MSDC_IOCON (0x04)
|
||||
#define MSDC_PS (0x08)
|
||||
#define MSDC_INT (0x0c)
|
||||
#define MSDC_INTEN (0x10)
|
||||
#define MSDC_FIFOCS (0x14)
|
||||
#define MSDC_TXDATA (0x18)
|
||||
#define MSDC_RXDATA (0x1c)
|
||||
#define SDC_CFG (0x30)
|
||||
#define SDC_CMD (0x34)
|
||||
#define SDC_ARG (0x38)
|
||||
#define SDC_STS (0x3c)
|
||||
#define SDC_RESP0 (0x40)
|
||||
#define SDC_RESP1 (0x44)
|
||||
#define SDC_RESP2 (0x48)
|
||||
#define SDC_RESP3 (0x4c)
|
||||
#define SDC_BLK_NUM (0x50)
|
||||
#define SDC_CSTS (0x58)
|
||||
#define SDC_CSTS_EN (0x5c)
|
||||
#define SDC_DCRC_STS (0x60)
|
||||
#define EMMC_CFG0 (0x70)
|
||||
#define EMMC_CFG1 (0x74)
|
||||
#define EMMC_STS (0x78)
|
||||
#define EMMC_IOCON (0x7c)
|
||||
#define SDC_ACMD_RESP (0x80)
|
||||
#define SDC_ACMD19_TRG (0x84)
|
||||
#define SDC_ACMD19_STS (0x88)
|
||||
#define MSDC_DMA_SA (0x90)
|
||||
#define MSDC_DMA_CA (0x94)
|
||||
#define MSDC_DMA_CTRL (0x98)
|
||||
#define MSDC_DMA_CFG (0x9c)
|
||||
#define MSDC_DBG_SEL (0xa0)
|
||||
#define MSDC_DBG_OUT (0xa4)
|
||||
#define MSDC_PATCH_BIT (0xb0)
|
||||
#define MSDC_PATCH_BIT0 MSDC_PATCH_BIT
|
||||
#define MSDC_PATCH_BIT1 (0xb4)
|
||||
#define MSDC_PAD_CTL0 (0xe0)
|
||||
#define MSDC_PAD_CTL1 (0xe4)
|
||||
#define MSDC_PAD_CTL2 (0xe8)
|
||||
#define MSDC_PAD_TUNE (0xec)
|
||||
#define MSDC_DAT_RDDLY0 (0xf0)
|
||||
#define MSDC_DAT_RDDLY1 (0xf4)
|
||||
#define MSDC_HW_DBG (0xf8)
|
||||
#define MSDC_VERSION (0x100)
|
||||
#define MSDC_ECO_VER (0x104)
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Register Mask */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
/* MSDC_CFG mask */
|
||||
#define MSDC_CFG_MODE (0x1 << 0) /* RW */
|
||||
#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
|
||||
#define MSDC_CFG_RST (0x1 << 2) /* RW */
|
||||
#define MSDC_CFG_PIO (0x1 << 3) /* RW */
|
||||
#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
|
||||
#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
|
||||
#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
|
||||
#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
|
||||
#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
|
||||
#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
|
||||
|
||||
/* MSDC_IOCON mask */
|
||||
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
|
||||
#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
|
||||
#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
|
||||
#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
|
||||
#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
|
||||
#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
|
||||
#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
|
||||
#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
|
||||
#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
|
||||
#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
|
||||
#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
|
||||
#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
|
||||
#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
|
||||
#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
|
||||
#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
|
||||
|
||||
/* MSDC_PS mask */
|
||||
#define MSDC_PS_CDEN (0x1 << 0) /* RW */
|
||||
#define MSDC_PS_CDSTS (0x1 << 1) /* R */
|
||||
#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
|
||||
#define MSDC_PS_DAT (0xff << 16) /* R */
|
||||
#define MSDC_PS_CMD (0x1 << 24) /* R */
|
||||
#define MSDC_PS_WP (0x1UL << 31) /* R */
|
||||
|
||||
/* MSDC_INT mask */
|
||||
#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
|
||||
#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
|
||||
#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
|
||||
#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
|
||||
#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
|
||||
#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
|
||||
#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
|
||||
#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
|
||||
#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
|
||||
#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
|
||||
#define MSDC_INT_CSTA (0x1 << 11) /* R */
|
||||
#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
|
||||
#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
|
||||
#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
|
||||
#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
|
||||
#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
|
||||
|
||||
/* MSDC_INTEN mask */
|
||||
#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
|
||||
#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
|
||||
#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
|
||||
#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
|
||||
#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
|
||||
#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
|
||||
#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
|
||||
#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
|
||||
#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
|
||||
#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
|
||||
#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
|
||||
#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
|
||||
#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
|
||||
#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
|
||||
#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
|
||||
#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
|
||||
|
||||
/* MSDC_FIFOCS mask */
|
||||
#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
|
||||
#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
|
||||
#define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
|
||||
|
||||
/* SDC_CFG mask */
|
||||
#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
|
||||
#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
|
||||
#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
|
||||
#define SDC_CFG_SDIO (0x1 << 19) /* RW */
|
||||
#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
|
||||
#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
|
||||
#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
|
||||
|
||||
/* SDC_CMD mask */
|
||||
#define SDC_CMD_OPC (0x3f << 0) /* RW */
|
||||
#define SDC_CMD_BRK (0x1 << 6) /* RW */
|
||||
#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
|
||||
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
|
||||
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
|
||||
#define SDC_CMD_RW (0x1 << 13) /* RW */
|
||||
#define SDC_CMD_STOP (0x1 << 14) /* RW */
|
||||
#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
|
||||
#define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
|
||||
#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
|
||||
#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
|
||||
|
||||
/* SDC_STS mask */
|
||||
#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
|
||||
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
|
||||
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
|
||||
|
||||
/* SDC_DCRC_STS mask */
|
||||
#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
|
||||
#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
|
||||
|
||||
/* EMMC_CFG0 mask */
|
||||
#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
|
||||
#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
|
||||
#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
|
||||
#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
|
||||
#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
|
||||
#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
|
||||
|
||||
/* EMMC_CFG1 mask */
|
||||
#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
|
||||
#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
|
||||
|
||||
/* EMMC_STS mask */
|
||||
#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
|
||||
#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
|
||||
#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
|
||||
#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
|
||||
#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
|
||||
#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
|
||||
#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
|
||||
|
||||
/* EMMC_IOCON mask */
|
||||
#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
|
||||
|
||||
/* SDC_ACMD19_TRG mask */
|
||||
#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
|
||||
|
||||
/* MSDC_DMA_CTRL mask */
|
||||
#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
|
||||
#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
|
||||
#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
|
||||
#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
|
||||
#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
|
||||
#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
|
||||
#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
|
||||
|
||||
/* MSDC_DMA_CFG mask */
|
||||
#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
|
||||
#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
|
||||
#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
|
||||
#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
|
||||
|
||||
/* MSDC_PATCH_BIT mask */
|
||||
#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
|
||||
#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
|
||||
#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
|
||||
#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
|
||||
#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
|
||||
#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
|
||||
#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
|
||||
#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
|
||||
#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
|
||||
#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
|
||||
#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
|
||||
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
|
||||
|
||||
/* MSDC_PATCH_BIT1 mask */
|
||||
#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
|
||||
#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
|
||||
|
||||
/* MSDC_PAD_CTL0 mask */
|
||||
#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_CTL1 mask */
|
||||
#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_CTL2 mask */
|
||||
#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
|
||||
#define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
|
||||
|
||||
/* MSDC_PAD_TUNE mask */
|
||||
#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
|
||||
#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
|
||||
#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
|
||||
#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
|
||||
#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
|
||||
|
||||
/* MSDC_DAT_RDDLY0/1 mask */
|
||||
#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
|
||||
#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
|
||||
#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
|
||||
#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
|
||||
|
||||
#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
|
||||
#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
|
||||
#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
|
||||
#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
|
||||
|
||||
#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
|
||||
#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
|
||||
#define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
|
||||
#define CARD_READY_FOR_DATA (1 << 8)
|
||||
#define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* Descriptor Structure */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
struct gpd {
|
||||
u32 hwo:1; /* could be changed by hw */
|
||||
u32 bdp:1;
|
||||
u32 rsv0:6;
|
||||
u32 chksum:8;
|
||||
u32 intr:1;
|
||||
u32 rsv1:15;
|
||||
void *next;
|
||||
void *ptr;
|
||||
u32 buflen:16;
|
||||
u32 extlen:8;
|
||||
u32 rsv2:8;
|
||||
u32 arg;
|
||||
u32 blknum;
|
||||
u32 cmd;
|
||||
};
|
||||
|
||||
struct bd {
|
||||
u32 eol:1;
|
||||
u32 rsv0:7;
|
||||
u32 chksum:8;
|
||||
u32 rsv1:1;
|
||||
u32 blkpad:1;
|
||||
u32 dwpad:1;
|
||||
u32 rsv2:13;
|
||||
void *next;
|
||||
void *ptr;
|
||||
u32 buflen:16;
|
||||
u32 rsv3:16;
|
||||
};
|
||||
|
||||
struct msdc_dma {
|
||||
struct gpd *gpd; /* pointer to gpd array */
|
||||
struct bd *bd; /* pointer to bd array */
|
||||
dma_addr_t gpd_addr; /* the physical address of gpd array */
|
||||
dma_addr_t bd_addr; /* the physical address of bd array */
|
||||
};
|
||||
|
||||
struct msdc_host {
|
||||
struct msdc_hw *hw;
|
||||
|
||||
struct mmc_host *mmc; /* mmc structure */
|
||||
struct mmc_command *cmd;
|
||||
struct mmc_data *data;
|
||||
struct mmc_request *mrq;
|
||||
int cmd_rsp;
|
||||
|
||||
int error;
|
||||
spinlock_t lock; /* mutex */
|
||||
struct semaphore sem;
|
||||
|
||||
u32 blksz; /* host block size */
|
||||
void __iomem *base; /* host base address */
|
||||
int id; /* host id */
|
||||
int pwr_ref; /* core power reference count */
|
||||
|
||||
u32 xfer_size; /* total transferred size */
|
||||
|
||||
struct msdc_dma dma; /* dma channel */
|
||||
u32 dma_xfer_size; /* dma transfer size in bytes */
|
||||
|
||||
u32 timeout_ns; /* data timeout ns */
|
||||
u32 timeout_clks; /* data timeout clks */
|
||||
|
||||
int irq; /* host interrupt */
|
||||
|
||||
struct delayed_work card_delaywork;
|
||||
|
||||
struct completion cmd_done;
|
||||
struct completion xfer_done;
|
||||
struct pm_message pm_state;
|
||||
|
||||
u32 mclk; /* mmc subsystem clock */
|
||||
u32 hclk; /* host clock speed */
|
||||
u32 sclk; /* SD/MS clock speed */
|
||||
u8 core_clkon; /* Host core clock on ? */
|
||||
u8 card_clkon; /* Card clock on ? */
|
||||
u8 core_power; /* core power */
|
||||
u8 power_mode; /* host power mode */
|
||||
u8 card_inserted; /* card inserted ? */
|
||||
u8 suspend; /* host suspended ? */
|
||||
u8 app_cmd; /* for app command */
|
||||
u32 app_cmd_arg;
|
||||
};
|
||||
|
||||
static inline void sdr_set_bits(void __iomem *reg, u32 bs)
|
||||
{
|
||||
u32 val = readl(reg);
|
||||
|
||||
val |= bs;
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
|
||||
{
|
||||
u32 val = readl(reg);
|
||||
|
||||
val &= ~bs;
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
|
||||
{
|
||||
unsigned int tv = readl(reg);
|
||||
|
||||
tv &= ~field;
|
||||
tv |= ((val) << (ffs((unsigned int)field) - 1));
|
||||
writel(tv, reg);
|
||||
}
|
||||
|
||||
static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
|
||||
{
|
||||
unsigned int tv = readl(reg);
|
||||
*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
|
||||
}
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user