iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/amd/display: Update BW alloc after new DMUB logic

Browse Source 
[WHY]
After introducing new DPIA NOTIFICATION we will need
to update the exiting BW allocation logic

[HOW]
Updated the BW alloc source and header files

Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mustapha Ghaddar 2022-12-07 14:01:36 -05:00 committed by Alex Deucher
parent 6b8701be1f
commit 857aa2beda
3 changed files with 49 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/dc_link.h
View File

@ -158,11 +158,11 @@ struct dc_panel_config {
struct dc_dpia_bw_alloc {
int sink_verified_bw; // The Verified BW that sink can allocated and use that has been verified already
int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
int padding_bw; // The Padding "Un-used" BW allocated by CM for padding reasons
int sink_max_bw; // The Max BW that sink can require/support
int estimated_bw; // The estimated available BW for this DPIA
int bw_granularity; // BW Granularity
bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM
bool response_ready; // Response ready from the CM side
};
/*

47
drivers/gpu/drm/amd/display/dc/link/link_dp_dpia_bw.h
View File

@ -26,13 +26,13 @@
#ifndef DC_INC_LINK_DP_DPIA_BW_H_
#define DC_INC_LINK_DP_DPIA_BW_H_
// XXX: TODO: Re-add for Phase 2
/* Number of Host Routers per motherboard is 2 and 2 DPIA per host router */
#define MAX_HR_NUM 2
struct dc_host_router_bw_alloc {
int max_bw[MAX_HR_NUM]; // The Max BW that each Host Router has available to be shared btw DPIAs
int total_estimated_bw[MAX_HR_NUM]; // The Total Verified and available BW that Host Router has
/*
* Host Router BW type
*/
enum bw_type {
HOST_ROUTER_BW_ESTIMATED,
HOST_ROUTER_BW_ALLOCATED,
HOST_ROUTER_BW_INVALID,
};
/*
@ -61,9 +61,40 @@ void set_usb4_req_bw_req(struct dc_link *link, int req_bw);
* find out the result of allocating on CM and update structs accordingly
*
* @link: pointer to the dc_link struct instance
* @bw: Allocated or Estimated BW depending on the result
* @result: Response type
*
* return: none
*/
void get_usb4_req_bw_resp(struct dc_link *link);
void get_usb4_req_bw_resp(struct dc_link *link, uint8_t bw, uint8_t result);
/*
* Return the response_ready flag from dc_link struct
*
* @link: pointer to the dc_link struct instance
*
* return: response_ready flag from dc_link struct
*/
bool get_cm_response_ready_flag(struct dc_link *link);
/*
* Get the Max Available BW or Max Estimated BW for each Host Router
*
* @link: pointer to the dc_link struct instance
* @type: ESTIMATD BW or MAX AVAILABLE BW
*
* return: response_ready flag from dc_link struct
*/
int get_host_router_total_bw(struct dc_link *link, uint8_t type);
/*
* Cleanup function for when the dpia is unplugged to reset struct
* and perform any required clean up
*
* @link: pointer to the dc_link struct instance
*
* return: none
*/
bool dpia_bw_alloc_unplug(struct dc_link *link);
#endif /* DC_INC_LINK_DP_DPIA_BW_H_ */

18
drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c
View File

@ -98,19 +98,19 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,
if (cmd.dpia_notify.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {
if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed) {
notify->bw_alloc_reply.estimated_bw =
cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
notify->bw_alloc_reply.allocated_bw =
cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed)
notify->result = DPIA_BW_REQ_FAILED;
} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded) {
else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded)
notify->result = DPIA_BW_REQ_SUCCESS;
notify->bw_alloc_reply.allocated_bw =
cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed) {
else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed)
notify->result = DPIA_EST_BW_CHANGED;
notify->bw_alloc_reply.estimated_bw =
cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed) {
else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed)
notify->result = DPIA_BW_ALLOC_CAPS_CHANGED;
}
}
break;
default: