Merge branch 'add-support-for-dp83tg720s-phy'
Oleksij Rempel says: ==================== add support for DP83TG720S PHY ==================== Link: https://lore.kernel.org/r/20231212054144.87527-1-o.rempel@pengutronix.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
85c2674d53
@ -394,6 +394,19 @@ config DP83TD510_PHY
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Support for the DP83TD510 Ethernet 10Base-T1L PHY. This PHY supports
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a 10M single pair Ethernet connection for up to 1000 meter cable.
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config DP83TG720_PHY
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tristate "Texas Instruments DP83TG720 Ethernet 1000Base-T1 PHY"
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help
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The DP83TG720S-Q1 is an automotive Ethernet physical layer
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transceiver compliant with IEEE 802.3bp and Open Alliance
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standards. It supports key functions necessary for
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transmitting and receiving data over both unshielded and
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shielded single twisted-pair cables. This device offers
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flexible xMII interface options, including support for both
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RGMII and SGMII MAC interfaces. It's suitable for applications
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requiring high-speed data transmission in automotive
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networking environments.
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config VITESSE_PHY
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tristate "Vitesse PHYs"
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help
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@ -57,6 +57,7 @@ obj-$(CONFIG_DP83867_PHY) += dp83867.o
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obj-$(CONFIG_DP83869_PHY) += dp83869.o
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obj-$(CONFIG_DP83TC811_PHY) += dp83tc811.o
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obj-$(CONFIG_DP83TD510_PHY) += dp83td510.o
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obj-$(CONFIG_DP83TG720_PHY) += dp83tg720.o
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obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
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obj-$(CONFIG_ICPLUS_PHY) += icplus.o
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obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
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188
drivers/net/phy/dp83tg720.c
Normal file
188
drivers/net/phy/dp83tg720.c
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@ -0,0 +1,188 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Driver for the Texas Instruments DP83TG720 PHY
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* Copyright (c) 2023 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#define DP83TG720S_PHY_ID 0x2000a284
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/* MDIO_MMD_VEND2 registers */
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#define DP83TG720S_MII_REG_10 0x10
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#define DP83TG720S_STS_MII_INT BIT(7)
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#define DP83TG720S_LINK_STATUS BIT(0)
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#define DP83TG720S_PHY_RESET 0x1f
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#define DP83TG720S_HW_RESET BIT(15)
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#define DP83TG720S_RGMII_DELAY_CTRL 0x602
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/* In RGMII mode, Enable or disable the internal delay for RXD */
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#define DP83TG720S_RGMII_RX_CLK_SEL BIT(1)
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/* In RGMII mode, Enable or disable the internal delay for TXD */
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#define DP83TG720S_RGMII_TX_CLK_SEL BIT(0)
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#define DP83TG720S_SQI_REG_1 0x871
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#define DP83TG720S_SQI_OUT_WORST GENMASK(7, 5)
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#define DP83TG720S_SQI_OUT GENMASK(3, 1)
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#define DP83TG720_SQI_MAX 7
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static int dp83tg720_config_aneg(struct phy_device *phydev)
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{
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/* Autoneg is not supported and this PHY supports only one speed.
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* We need to care only about master/slave configuration if it was
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* changed by user.
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*/
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return genphy_c45_pma_baset1_setup_master_slave(phydev);
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}
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static int dp83tg720_read_status(struct phy_device *phydev)
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{
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u16 phy_sts;
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int ret;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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/* Most of Clause 45 registers are not present, so we can't use
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* genphy_c45_read_status() here.
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*/
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phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10);
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phydev->link = !!(phy_sts & DP83TG720S_LINK_STATUS);
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if (!phydev->link) {
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/* According to the "DP83TC81x, DP83TG72x Software
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* Implementation Guide", the PHY needs to be reset after a
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* link loss or if no link is created after at least 100ms.
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*
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* Currently we are polling with the PHY_STATE_TIME (1000ms)
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* interval, which is still enough for not automotive use cases.
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*/
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ret = phy_init_hw(phydev);
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if (ret)
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return ret;
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/* After HW reset we need to restore master/slave configuration.
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*/
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ret = dp83tg720_config_aneg(phydev);
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if (ret)
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return ret;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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} else {
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/* PMA/PMD control 1 register (Register 1.0) is present, but it
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* doesn't contain the link speed information.
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* So genphy_c45_read_pma() can't be used here.
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*/
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ret = genphy_c45_pma_baset1_read_master_slave(phydev);
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if (ret)
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return ret;
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_1000;
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}
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return 0;
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}
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static int dp83tg720_get_sqi(struct phy_device *phydev)
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{
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int ret;
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if (!phydev->link)
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return 0;
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1);
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if (ret < 0)
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return ret;
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return FIELD_GET(DP83TG720S_SQI_OUT, ret);
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}
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static int dp83tg720_get_sqi_max(struct phy_device *phydev)
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{
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return DP83TG720_SQI_MAX;
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}
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static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)
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{
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u16 rgmii_delay_mask;
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u16 rgmii_delay = 0;
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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rgmii_delay = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL |
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DP83TG720S_RGMII_TX_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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rgmii_delay = DP83TG720S_RGMII_TX_CLK_SEL;
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break;
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default:
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return 0;
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}
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rgmii_delay_mask = DP83TG720S_RGMII_RX_CLK_SEL |
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DP83TG720S_RGMII_TX_CLK_SEL;
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return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
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DP83TG720S_RGMII_DELAY_CTRL, rgmii_delay_mask,
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rgmii_delay);
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}
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static int dp83tg720_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Software Restart is not enough to recover from a link failure.
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* Using Hardware Reset instead.
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*/
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ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
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if (ret)
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return ret;
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/* Wait until MDC can be used again.
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* The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1
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* Automotive Ethernet PHY with SGMII and RGMII" datasheet.
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*/
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usleep_range(1000, 2000);
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if (phy_interface_is_rgmii(phydev))
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return dp83tg720_config_rgmii_delay(phydev);
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return 0;
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}
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static struct phy_driver dp83tg720_driver[] = {
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{
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PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID),
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.name = "TI DP83TG720S",
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.config_aneg = dp83tg720_config_aneg,
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.read_status = dp83tg720_read_status,
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.get_features = genphy_c45_pma_read_ext_abilities,
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.config_init = dp83tg720_config_init,
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.get_sqi = dp83tg720_get_sqi,
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.get_sqi_max = dp83tg720_get_sqi_max,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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} };
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module_phy_driver(dp83tg720_driver);
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static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {
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{ PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83TG720S PHY driver");
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MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
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MODULE_LICENSE("GPL");
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@ -919,6 +919,79 @@ int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)
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}
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EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_abilities);
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/**
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* genphy_c45_pma_read_ext_abilities - read supported link modes from PMA
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* @phydev: target phy_device struct
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*
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* Read the supported link modes from the PMA/PMD extended ability register
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* (Register 1.11).
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*/
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int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBLRM);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKX4);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKR);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BKX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_100BTX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_100BTX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10BT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10BT);
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if (val & MDIO_PMA_EXTABLE_NBT) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
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MDIO_PMA_NG_EXTABLE);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_2_5GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_5GBT);
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}
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if (val & MDIO_PMA_EXTABLE_BT1) {
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val = genphy_c45_pma_baset1_read_abilities(phydev);
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if (val < 0)
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return val;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_pma_read_ext_abilities);
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/**
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* genphy_c45_pma_read_abilities - read supported link modes from PMA
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* @phydev: target phy_device struct
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@ -962,63 +1035,9 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev)
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val & MDIO_PMA_STAT2_10GBER);
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if (val & MDIO_PMA_STAT2_EXTABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
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val = genphy_c45_pma_read_ext_abilities(phydev);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBLRM);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKX4);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10GBKR);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_1000BKX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_100BTX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_100BTX);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10BT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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phydev->supported,
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val & MDIO_PMA_EXTABLE_10BT);
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if (val & MDIO_PMA_EXTABLE_NBT) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
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MDIO_PMA_NG_EXTABLE);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_2_5GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_5GBT);
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}
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if (val & MDIO_PMA_EXTABLE_BT1) {
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val = genphy_c45_pma_baset1_read_abilities(phydev);
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if (val < 0)
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return val;
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}
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}
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/* This is optional functionality. If not supported, we may get an error
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@ -1866,6 +1866,7 @@ int genphy_c45_an_config_aneg(struct phy_device *phydev);
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int genphy_c45_an_disable_aneg(struct phy_device *phydev);
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int genphy_c45_read_mdix(struct phy_device *phydev);
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int genphy_c45_pma_read_abilities(struct phy_device *phydev);
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int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev);
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int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev);
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int genphy_c45_read_eee_abilities(struct phy_device *phydev);
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int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev);
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