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drm/amdgpu: add ih 6.1 registers

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Add new registers.

v2: updates (Alex)

Signed-off-by: Ben Li <ben.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ben Li 2023-07-14 15:41:14 -04:00 committed by Alex Deucher
parent eff7a442c1
commit 85c391abd2
2 changed files with 1298 additions and 0 deletions
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279
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_offset.h Normal file
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/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _osssys_6_1_0_OFFSET_HEADER
#define _osssys_6_1_0_OFFSET_HEADER
// addressBlock: osssys_osssysdec
// base address: 0x4280
#define regIH_VMID_0_LUT 0x0000
#define regIH_VMID_0_LUT_BASE_IDX 0
#define regIH_VMID_1_LUT 0x0001
#define regIH_VMID_1_LUT_BASE_IDX 0
#define regIH_VMID_2_LUT 0x0002
#define regIH_VMID_2_LUT_BASE_IDX 0
#define regIH_VMID_3_LUT 0x0003
#define regIH_VMID_3_LUT_BASE_IDX 0
#define regIH_VMID_4_LUT 0x0004
#define regIH_VMID_4_LUT_BASE_IDX 0
#define regIH_VMID_5_LUT 0x0005
#define regIH_VMID_5_LUT_BASE_IDX 0
#define regIH_VMID_6_LUT 0x0006
#define regIH_VMID_6_LUT_BASE_IDX 0
#define regIH_VMID_7_LUT 0x0007
#define regIH_VMID_7_LUT_BASE_IDX 0
#define regIH_VMID_8_LUT 0x0008
#define regIH_VMID_8_LUT_BASE_IDX 0
#define regIH_VMID_9_LUT 0x0009
#define regIH_VMID_9_LUT_BASE_IDX 0
#define regIH_VMID_10_LUT 0x000a
#define regIH_VMID_10_LUT_BASE_IDX 0
#define regIH_VMID_11_LUT 0x000b
#define regIH_VMID_11_LUT_BASE_IDX 0
#define regIH_VMID_12_LUT 0x000c
#define regIH_VMID_12_LUT_BASE_IDX 0
#define regIH_VMID_13_LUT 0x000d
#define regIH_VMID_13_LUT_BASE_IDX 0
#define regIH_VMID_14_LUT 0x000e
#define regIH_VMID_14_LUT_BASE_IDX 0
#define regIH_VMID_15_LUT 0x000f
#define regIH_VMID_15_LUT_BASE_IDX 0
#define regIH_VMID_0_LUT_MM 0x0010
#define regIH_VMID_0_LUT_MM_BASE_IDX 0
#define regIH_VMID_1_LUT_MM 0x0011
#define regIH_VMID_1_LUT_MM_BASE_IDX 0
#define regIH_VMID_2_LUT_MM 0x0012
#define regIH_VMID_2_LUT_MM_BASE_IDX 0
#define regIH_VMID_3_LUT_MM 0x0013
#define regIH_VMID_3_LUT_MM_BASE_IDX 0
#define regIH_VMID_4_LUT_MM 0x0014
#define regIH_VMID_4_LUT_MM_BASE_IDX 0
#define regIH_VMID_5_LUT_MM 0x0015
#define regIH_VMID_5_LUT_MM_BASE_IDX 0
#define regIH_VMID_6_LUT_MM 0x0016
#define regIH_VMID_6_LUT_MM_BASE_IDX 0
#define regIH_VMID_7_LUT_MM 0x0017
#define regIH_VMID_7_LUT_MM_BASE_IDX 0
#define regIH_VMID_8_LUT_MM 0x0018
#define regIH_VMID_8_LUT_MM_BASE_IDX 0
#define regIH_VMID_9_LUT_MM 0x0019
#define regIH_VMID_9_LUT_MM_BASE_IDX 0
#define regIH_VMID_10_LUT_MM 0x001a
#define regIH_VMID_10_LUT_MM_BASE_IDX 0
#define regIH_VMID_11_LUT_MM 0x001b
#define regIH_VMID_11_LUT_MM_BASE_IDX 0
#define regIH_VMID_12_LUT_MM 0x001c
#define regIH_VMID_12_LUT_MM_BASE_IDX 0
#define regIH_VMID_13_LUT_MM 0x001d
#define regIH_VMID_13_LUT_MM_BASE_IDX 0
#define regIH_VMID_14_LUT_MM 0x001e
#define regIH_VMID_14_LUT_MM_BASE_IDX 0
#define regIH_VMID_15_LUT_MM 0x001f
#define regIH_VMID_15_LUT_MM_BASE_IDX 0
#define regIH_COOKIE_0 0x0020
#define regIH_COOKIE_0_BASE_IDX 0
#define regIH_COOKIE_1 0x0021
#define regIH_COOKIE_1_BASE_IDX 0
#define regIH_COOKIE_2 0x0022
#define regIH_COOKIE_2_BASE_IDX 0
#define regIH_COOKIE_3 0x0023
#define regIH_COOKIE_3_BASE_IDX 0
#define regIH_COOKIE_4 0x0024
#define regIH_COOKIE_4_BASE_IDX 0
#define regIH_COOKIE_5 0x0025
#define regIH_COOKIE_5_BASE_IDX 0
#define regIH_COOKIE_6 0x0026
#define regIH_COOKIE_6_BASE_IDX 0
#define regIH_COOKIE_7 0x0027
#define regIH_COOKIE_7_BASE_IDX 0
#define regIH_REGISTER_LAST_PART0 0x003f
#define regIH_REGISTER_LAST_PART0_BASE_IDX 0
#define regIH_RB_CNTL 0x0080
#define regIH_RB_CNTL_BASE_IDX 0
#define regIH_RB_RPTR 0x0081
#define regIH_RB_RPTR_BASE_IDX 0
#define regIH_RB_WPTR 0x0082
#define regIH_RB_WPTR_BASE_IDX 0
#define regIH_RB_BASE 0x0083
#define regIH_RB_BASE_BASE_IDX 0
#define regIH_RB_BASE_HI 0x0084
#define regIH_RB_BASE_HI_BASE_IDX 0
#define regIH_RB_WPTR_ADDR_HI 0x0085
#define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0
#define regIH_RB_WPTR_ADDR_LO 0x0086
#define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0
#define regIH_DOORBELL_RPTR 0x0087
#define regIH_DOORBELL_RPTR_BASE_IDX 0
#define regIH_DOORBELL_RETRY_CAM 0x0088
#define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0
#define regIH_RB_CNTL_RING1 0x008c
#define regIH_RB_CNTL_RING1_BASE_IDX 0
#define regIH_RB_RPTR_RING1 0x008d
#define regIH_RB_RPTR_RING1_BASE_IDX 0
#define regIH_RB_WPTR_RING1 0x008e
#define regIH_RB_WPTR_RING1_BASE_IDX 0
#define regIH_RB_BASE_RING1 0x008f
#define regIH_RB_BASE_RING1_BASE_IDX 0
#define regIH_RB_BASE_HI_RING1 0x0090
#define regIH_RB_BASE_HI_RING1_BASE_IDX 0
#define regIH_DOORBELL_RPTR_RING1 0x0093
#define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0
#define regIH_RETRY_CAM_ACK 0x00a4
#define regIH_RETRY_CAM_ACK_BASE_IDX 0
#define regIH_VERSION 0x00a5
#define regIH_VERSION_BASE_IDX 0
#define regIH_CNTL 0x00a8
#define regIH_CNTL_BASE_IDX 0
#define regIH_CLK_CTRL 0x00a9
#define regIH_CLK_CTRL_BASE_IDX 0
#define regIH_STORM_CLIENT_LIST_CNTL 0x00aa
#define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0
#define regIH_LIMIT_INT_RATE_CNTL 0x00ab
#define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0
#define regIH_RETRY_INT_CAM_CNTL 0x00ac
#define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0
#define regIH_MEM_POWER_CTRL 0x00ad
#define regIH_MEM_POWER_CTRL_BASE_IDX 0
#define regIH_MEM_POWER_CTRL2 0x00ae
#define regIH_MEM_POWER_CTRL2_BASE_IDX 0
#define regIH_CNTL2 0x00c1
#define regIH_CNTL2_BASE_IDX 0
#define regIH_STATUS 0x00c2
#define regIH_STATUS_BASE_IDX 0
#define regIH_PERFMON_CNTL 0x00c3
#define regIH_PERFMON_CNTL_BASE_IDX 0
#define regIH_PERFCOUNTER0_RESULT 0x00c4
#define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0
#define regIH_PERFCOUNTER1_RESULT 0x00c5
#define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7
#define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8
#define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0
#define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9
#define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0
#define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca
#define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0
#define regIH_DSM_MATCH_DATA_CONTROL 0x00cb
#define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0
#define regIH_DSM_MATCH_FCN_ID 0x00cc
#define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0
#define regIH_VF_RB_STATUS 0x00ce
#define regIH_VF_RB_STATUS_BASE_IDX 0
#define regIH_VF_RB_STATUS2 0x00cf
#define regIH_VF_RB_STATUS2_BASE_IDX 0
#define regIH_VF_RB1_STATUS 0x00d0
#define regIH_VF_RB1_STATUS_BASE_IDX 0
#define regIH_VF_RB1_STATUS2 0x00d1
#define regIH_VF_RB1_STATUS2_BASE_IDX 0
#define regIH_RB_STATUS 0x00d4
#define regIH_RB_STATUS_BASE_IDX 0
#define regIH_INT_FLOOD_CNTL 0x00d5
#define regIH_INT_FLOOD_CNTL_BASE_IDX 0
#define regIH_RB0_INT_FLOOD_STATUS 0x00d6
#define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_RB1_INT_FLOOD_STATUS 0x00d7
#define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_INT_FLOOD_STATUS 0x00d9
#define regIH_INT_FLOOD_STATUS_BASE_IDX 0
#define regIH_INT_FLAGS 0x00dc
#define regIH_INT_FLAGS_BASE_IDX 0
#define regIH_LAST_INT_INFO0 0x00dd
#define regIH_LAST_INT_INFO0_BASE_IDX 0
#define regIH_LAST_INT_INFO1 0x00de
#define regIH_LAST_INT_INFO1_BASE_IDX 0
#define regIH_LAST_INT_INFO2 0x00df
#define regIH_LAST_INT_INFO2_BASE_IDX 0
#define regIH_SCRATCH 0x00e0
#define regIH_SCRATCH_BASE_IDX 0
#define regIH_CLIENT_CREDIT_ERROR 0x00e1
#define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0
#define regIH_GPU_IOV_VIOLATION_LOG 0x00e2
#define regIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
#define regIH_GPU_IOV_VIOLATION_LOG2 0x00e3
#define regIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0
#define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4
#define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0
#define regIH_CREDIT_STATUS 0x00e5
#define regIH_CREDIT_STATUS_BASE_IDX 0
#define regIH_MMHUB_ERROR 0x00e6
#define regIH_MMHUB_ERROR_BASE_IDX 0
#define regIH_VF_RB_STATUS3 0x00ea
#define regIH_VF_RB_STATUS3_BASE_IDX 0
#define regIH_VF_RB_STATUS4 0x00eb
#define regIH_VF_RB_STATUS4_BASE_IDX 0
#define regIH_VF_RB1_STATUS3 0x00ec
#define regIH_VF_RB1_STATUS3_BASE_IDX 0
#define regIH_MSI_STORM_CTRL 0x00f1
#define regIH_MSI_STORM_CTRL_BASE_IDX 0
#define regIH_MSI_STORM_CLIENT_INDEX 0x00f2
#define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0
#define regIH_MSI_STORM_CLIENT_DATA 0x00f3
#define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0
#define regIH_REGISTER_LAST_PART2 0x00ff
#define regIH_REGISTER_LAST_PART2_BASE_IDX 0
#define regSEM_MAILBOX 0x010a
#define regSEM_MAILBOX_BASE_IDX 0
#define regSEM_MAILBOX_CLEAR 0x010b
#define regSEM_MAILBOX_CLEAR_BASE_IDX 0
#define regSEM_REGISTER_LAST_PART2 0x017f
#define regSEM_REGISTER_LAST_PART2_BASE_IDX 0
#define regIH_ACTIVE_FCN_ID 0x0180
#define regIH_ACTIVE_FCN_ID_BASE_IDX 0
#define regIH_VIRT_RESET_REQ 0x0181
#define regIH_VIRT_RESET_REQ_BASE_IDX 0
#define regIH_CLIENT_CFG 0x0184
#define regIH_CLIENT_CFG_BASE_IDX 0
#define regIH_RING1_CLIENT_CFG_INDEX 0x0185
#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX 0
#define regIH_RING1_CLIENT_CFG_DATA 0x0186
#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX 0
#define regIH_CLIENT_CFG_INDEX 0x0188
#define regIH_CLIENT_CFG_INDEX_BASE_IDX 0
#define regIH_CLIENT_CFG_DATA 0x0189
#define regIH_CLIENT_CFG_DATA_BASE_IDX 0
#define regIH_CLIENT_CFG_DATA2 0x018a
#define regIH_CLIENT_CFG_DATA2_BASE_IDX 0
#define regIH_CID_REMAP_INDEX 0x018b
#define regIH_CID_REMAP_INDEX_BASE_IDX 0
#define regIH_CID_REMAP_DATA 0x018c
#define regIH_CID_REMAP_DATA_BASE_IDX 0
#define regIH_CHICKEN 0x018d
#define regIH_CHICKEN_BASE_IDX 0
#define regIH_MMHUB_CNTL 0x018e
#define regIH_MMHUB_CNTL_BASE_IDX 0
#define regIH_INT_DROP_CNTL 0x018f
#define regIH_INT_DROP_CNTL_BASE_IDX 0
#define regIH_INT_DROP_MATCH_VALUE0 0x0190
#define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0
#define regIH_INT_DROP_MATCH_VALUE1 0x0191
#define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0
#define regIH_INT_DROP_MATCH_MASK0 0x0192
#define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0
#define regIH_INT_DROP_MATCH_MASK1 0x0193
#define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0
#define regIH_REGISTER_LAST_PART1 0x019f
#define regIH_REGISTER_LAST_PART1_BASE_IDX 0
#endif

1019
drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_1_0_sh_mask.h Normal file
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