drm/i915/selftests: Check that registers are preserved between virtual engines
Make sure that we copy across the registers from one engine to the next, as we hop around a virtual engine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191010110252.17289-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
bd9bec5b6a
commit
86027e312c
@ -19,6 +19,33 @@
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#include "gem/selftests/igt_gem_utils.h"
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#include "gem/selftests/mock_context.h"
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static struct i915_vma *create_scratch(struct intel_gt *gt)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int err;
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obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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return vma;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
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if (err) {
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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return vma;
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}
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static int live_sanitycheck(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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@ -2076,6 +2103,158 @@ static int live_virtual_mask(void *arg)
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return 0;
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}
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static int preserved_virtual_engine(struct drm_i915_private *i915,
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struct intel_engine_cs **siblings,
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unsigned int nsibling)
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{
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#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
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struct i915_request *last = NULL;
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struct i915_gem_context *ctx;
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struct intel_context *ve;
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struct i915_vma *scratch;
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struct igt_live_test t;
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const int num_gpr = 16 * 2; /* each GPR is 2 dwords */
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unsigned int n;
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int err = 0;
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ctx = kernel_context(i915);
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if (!ctx)
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return -ENOMEM;
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scratch = create_scratch(siblings[0]->gt);
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if (IS_ERR(scratch)) {
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err = PTR_ERR(scratch);
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goto out_close;
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}
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ve = intel_execlists_create_virtual(ctx, siblings, nsibling);
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if (IS_ERR(ve)) {
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err = PTR_ERR(ve);
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goto out_scratch;
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}
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err = intel_context_pin(ve);
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if (err)
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goto out_put;
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err = igt_live_test_begin(&t, i915, __func__, ve->engine->name);
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if (err)
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goto out_unpin;
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for (n = 0; n < num_gpr; n++) {
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struct intel_engine_cs *engine = siblings[n % nsibling];
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struct i915_request *rq;
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u32 *cs;
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rq = i915_request_create(ve);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_end;
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}
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i915_request_put(last);
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last = i915_request_get(rq);
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cs = intel_ring_begin(rq, 8);
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if (IS_ERR(cs)) {
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i915_request_add(rq);
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err = PTR_ERR(cs);
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goto out_end;
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}
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*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
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*cs++ = CS_GPR(engine, n);
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*cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32);
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*cs++ = 0;
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = CS_GPR(engine, (n + 1) % num_gpr);
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*cs++ = n + 1;
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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/* Restrict this request to run on a particular engine */
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rq->execution_mask = engine->mask;
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i915_request_add(rq);
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}
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if (i915_request_wait(last, 0, HZ / 5) < 0) {
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err = -ETIME;
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} else {
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u32 *map = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
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for (n = 0; n < num_gpr; n++) {
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if (map[n] != n) {
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pr_err("Incorrect value[%d] found for GPR[%d]\n",
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map[n], n);
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err = -EINVAL;
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break;
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}
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}
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i915_gem_object_unpin_map(scratch->obj);
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}
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out_end:
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if (igt_live_test_end(&t))
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err = -EIO;
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i915_request_put(last);
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out_unpin:
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intel_context_unpin(ve);
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out_put:
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intel_context_put(ve);
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out_scratch:
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i915_vma_unpin_and_release(&scratch, 0);
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out_close:
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kernel_context_close(ctx);
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return err;
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#undef CS_GPR
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}
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static int live_virtual_preserved(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *siblings[MAX_ENGINE_INSTANCE + 1];
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struct intel_gt *gt = &i915->gt;
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unsigned int class, inst;
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/*
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* Check that the context image retains non-privileged (user) registers
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* from one engine to the next. For this we check that the CS_GPR
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* are preserved.
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*/
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if (USES_GUC_SUBMISSION(i915))
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return 0;
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/* As we use CS_GPR we cannot run before they existed on all engines. */
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if (INTEL_GEN(i915) < 9)
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return 0;
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for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
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int nsibling, err;
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nsibling = 0;
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for (inst = 0; inst <= MAX_ENGINE_INSTANCE; inst++) {
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if (!gt->engine_class[class][inst])
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continue;
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siblings[nsibling++] = gt->engine_class[class][inst];
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}
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if (nsibling < 2)
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continue;
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err = preserved_virtual_engine(i915, siblings, nsibling);
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if (err)
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return err;
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}
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return 0;
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}
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static int bond_virtual_engine(struct drm_i915_private *i915,
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unsigned int class,
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struct intel_engine_cs **siblings,
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@ -2277,6 +2456,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
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SUBTEST(live_preempt_smoke),
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SUBTEST(live_virtual_engine),
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SUBTEST(live_virtual_mask),
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SUBTEST(live_virtual_preserved),
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SUBTEST(live_virtual_bond),
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};
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