clk: mediatek: Remove MT8183 unused clock
Remove MT8183 sspm clock Signed-off-by: Erin Lo <erin.lo@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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0fd4939ac1
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860690a93e
@ -395,14 +395,6 @@ static const char * const atb_parents[] = {
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"syspll_d5"
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"syspll_d5"
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};
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};
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static const char * const sspm_parents[] = {
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"clk26m",
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"univpll_d2_d4",
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"syspll_d2_d2",
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"univpll_d2_d2",
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"syspll_d3"
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};
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static const char * const dpi0_parents[] = {
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static const char * const dpi0_parents[] = {
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"clk26m",
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"clk26m",
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"tvdpll_d2",
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"tvdpll_d2",
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@ -606,9 +598,6 @@ static const struct mtk_mux top_muxes[] = {
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
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atb_parents, 0xa0,
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atb_parents, 0xa0,
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0xa4, 0xa8, 0, 2, 7, 0x004, 24),
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0xa4, 0xa8, 0, 2, 7, 0x004, 24),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel",
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sspm_parents, 0xa0,
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0xa4, 0xa8, 8, 3, 15, 0x004, 25),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
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MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
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dpi0_parents, 0xa0,
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dpi0_parents, 0xa0,
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0xa4, 0xa8, 16, 4, 23, 0x004, 26),
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0xa4, 0xa8, 16, 4, 23, 0x004, 26),
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@ -947,12 +936,8 @@ static const struct mtk_gate infra_clks[] = {
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"fufs_sel", 13),
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"fufs_sel", 13),
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GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
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GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
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"axi_sel", 14),
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"axi_sel", 14),
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GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm",
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"sspm_sel", 15),
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GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
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GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
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"axi_sel", 16),
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"axi_sel", 16),
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GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
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"axi_sel", 17),
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GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
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GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
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"i2c_sel", 18),
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"i2c_sel", 18),
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GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
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GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
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@ -986,10 +971,6 @@ static const struct mtk_gate infra_clks[] = {
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"msdc50_0_sel", 1),
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"msdc50_0_sel", 1),
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GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
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GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
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"msdc50_0_sel", 2),
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"msdc50_0_sel", 2),
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GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
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"f_f26m_ck", 3),
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GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
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"f_f26m_ck", 4),
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GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
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GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
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"axi_sel", 5),
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"axi_sel", 5),
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GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
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GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
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