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net: wangxun: clean up the code

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Convert various mult-bit fields to be defined using GENMASK/FIELD_PREP.
Simplify the code with the ternary operator.

Signed-off-by: Mengyuan Lou <mengyuanlou@net-swift.com>
Reviewed-by: Simon Horman <simon.horman@corigine.com>
Link: https://lore.kernel.org/r/20230116103839.84087-1-mengyuanlou@net-swift.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Mengyuan Lou 2023-01-16 18:38:39 +08:00 committed by Jakub Kicinski
parent f3a1e0c896
commit 860edff562
4 changed files with 24 additions and 33 deletions
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22
drivers/net/ethernet/wangxun/libwx/wx_hw.c
View File

@ -76,15 +76,11 @@ EXPORT_SYMBOL(wx_check_flash_load);
void wx_control_hw(struct wx *wx, bool drv)
{
if (drv) {
/* Let firmware know the driver has taken over */
wr32m(wx, WX_CFG_PORT_CTL,
WX_CFG_PORT_CTL_DRV_LOAD, WX_CFG_PORT_CTL_DRV_LOAD);
} else {
/* Let firmware take over control of hw */
wr32m(wx, WX_CFG_PORT_CTL,
WX_CFG_PORT_CTL_DRV_LOAD, 0);
}
/* True : Let firmware know the driver has taken over
* False : Let firmware take over control of hw
*/
wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD,
drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0);
}
EXPORT_SYMBOL(wx_control_hw);
@ -575,8 +571,8 @@ static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools,
wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low);
wr32m(wx, WX_PSR_MAC_SWC_AD_H,
(WX_PSR_MAC_SWC_AD_H_AD(~0) |
WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) |
(WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
WX_PSR_MAC_SWC_AD_H_AV),
rar_high);
@ -611,8 +607,8 @@ static int wx_clear_rar(struct wx *wx, u32 index)
wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
wr32m(wx, WX_PSR_MAC_SWC_AD_H,
(WX_PSR_MAC_SWC_AD_H_AD(~0) |
WX_PSR_MAC_SWC_AD_H_ADTYPE(~0) |
(WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) |
WX_PSR_MAC_SWC_AD_H_ADTYPE(1) |
WX_PSR_MAC_SWC_AD_H_AV),
0);

15
drivers/net/ethernet/wangxun/libwx/wx_type.h
View File

@ -4,6 +4,8 @@
#ifndef _WX_TYPE_H_
#define _WX_TYPE_H_
#include <linux/bitfield.h>
/* Vendor ID */
#ifndef PCI_VENDOR_ID_WANGXUN
#define PCI_VENDOR_ID_WANGXUN 0x8088
@ -36,12 +38,11 @@
#define WX_SPI_CMD 0x10104
#define WX_SPI_CMD_READ_DWORD 0x1
#define WX_SPI_CLK_DIV 0x3
#define WX_SPI_CMD_CMD(_v) (((_v) & 0x7) << 28)
#define WX_SPI_CMD_CLK(_v) (((_v) & 0x7) << 25)
#define WX_SPI_CMD_ADDR(_v) (((_v) & 0xFFFFFF))
#define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
#define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
#define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
#define WX_SPI_DATA 0x10108
#define WX_SPI_DATA_BYPASS BIT(31)
#define WX_SPI_DATA_STATUS(_v) (((_v) & 0xFF) << 16)
#define WX_SPI_DATA_OP_DONE BIT(0)
#define WX_SPI_STATUS 0x1010C
#define WX_SPI_STATUS_OPDONE BIT(0)
@ -113,8 +114,8 @@
/* mac switcher */
#define WX_PSR_MAC_SWC_AD_L 0x16200
#define WX_PSR_MAC_SWC_AD_H 0x16204
#define WX_PSR_MAC_SWC_AD_H_AD(v) (((v) & 0xFFFF))
#define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) (((v) & 0x1) << 30)
#define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
#define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
#define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
#define WX_PSR_MAC_SWC_VM_L 0x16208
#define WX_PSR_MAC_SWC_VM_H 0x1620C
@ -134,7 +135,7 @@
#define WX_MAC_TX_CFG 0x11000
#define WX_MAC_TX_CFG_TE BIT(0)
#define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
#define WX_MAC_TX_CFG_SPEED_1G (0x3 << 29)
#define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
#define WX_MAC_RX_CFG 0x11004
#define WX_MAC_RX_CFG_RE BIT(0)
#define WX_MAC_RX_CFG_JE BIT(8)

8
drivers/net/ethernet/wangxun/ngbe/ngbe_hw.c
View File

@ -49,12 +49,8 @@ static int ngbe_reset_misc(struct wx *wx)
void ngbe_sfp_modules_txrx_powerctl(struct wx *wx, bool swi)
{
if (swi)
/* gpio0 is used to power on control*/
wr32(wx, NGBE_GPIO_DR, 0);
else
/* gpio0 is used to power off control*/
wr32(wx, NGBE_GPIO_DR, NGBE_GPIO_DR_0);
/* gpio0 is used to power on control . 0 is on */
wr32(wx, NGBE_GPIO_DR, swi ? 0 : NGBE_GPIO_DR_0);
}
/**

12
drivers/net/ethernet/wangxun/ngbe/ngbe_type.h
View File

@ -49,7 +49,6 @@
#define NGBE_SPI_ILDR_STATUS 0x10120
#define NGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */
#define NGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */
#define NGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */
/* Checksum and EEPROM pointers */
#define NGBE_CALSUM_COMMAND 0xE9
@ -62,12 +61,11 @@
/* mdio access */
#define NGBE_MSCA 0x11200
#define NGBE_MSCA_RA(v) ((0xFFFF & (v)))
#define NGBE_MSCA_PA(v) ((0x1F & (v)) << 16)
#define NGBE_MSCA_DA(v) ((0x1F & (v)) << 21)
#define NGBE_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
#define NGBE_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
#define NGBE_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
#define NGBE_MSCC 0x11204
#define NGBE_MSCC_DATA(v) ((0xFFFF & (v)))
#define NGBE_MSCC_CMD(v) ((0x3 & (v)) << 16)
#define NGBE_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
enum NGBE_MSCA_CMD_value {
NGBE_MSCA_CMD_RSV = 0,
@ -78,7 +76,7 @@ enum NGBE_MSCA_CMD_value {
#define NGBE_MSCC_SADDR BIT(18)
#define NGBE_MSCC_BUSY BIT(22)
#define NGBE_MDIO_CLK(v) ((0x7 & (v)) << 19)
#define NGBE_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
/* Media-dependent registers. */
#define NGBE_MDIO_CLAUSE_SELECT 0x11220