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Merge tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

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SoCFPGA dts updates for v6.2
- Use the "clk-phase-sd-hs" property for SDMMC
- Remove the "clk-phase" fom the sdmmc_clk that is no longer used
- Clean dtschema for mmc node
- Increase NAND partition for Arria10

* tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
  arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
  arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
  arm: dts: socfpga: align mmc node names with dtschema
  ARM: dts: socfpga: arria10: Increase NAND boot partition size

Link: https://lore.kernel.org/r/20221121163259.341974-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-11-22 23:00:03 +01:00
parent 6721cf8585 31354121bf
commit 867531d95c
14 changed files with 19 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/socfpga.dtsi
View File

@ -453,7 +453,6 @@
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 8>; clk-gate = <0xa0 8>;
clk-phase = <0 135>;
}; };
sdmmc_clk_divided: sdmmc_clk_divided { sdmmc_clk_divided: sdmmc_clk_divided {
@ -755,7 +754,7 @@
reg = <0xff800000 0x1000>; reg = <0xff800000 0x1000>;
}; };
mmc: dwmmc0@ff704000 { mmc: mmc@ff704000 {
compatible = "altr,socfpga-dw-mshc"; compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>; reg = <0xff704000 0x1000>;
interrupts = <0 139 4>; interrupts = <0 139 4>;
@ -765,6 +764,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>; resets = <&rst SDMMC_RESET>;
altr,sysmgr-syscon = <&sysmgr 0x108 3>;
status = "disabled"; status = "disabled";
}; };

4
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -365,7 +365,6 @@
compatible = "altr,socfpga-a10-gate-clk"; compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>; clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>; clk-gate = <0xC8 5>;
clk-phase = <0 135>;
}; };
qspi_clk: qspi_clk { qspi_clk: qspi_clk {
@ -656,7 +655,7 @@
arm,shared-override; arm,shared-override;
}; };
mmc: dwmmc0@ff808000 { mmc: mmc@ff808000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "altr,socfpga-dw-mshc"; compatible = "altr,socfpga-dw-mshc";
@ -666,6 +665,7 @@
clocks = <&l4_mp_clk>, <&sdmmc_clk>; clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
resets = <&rst SDMMC_RESET>; resets = <&rst SDMMC_RESET>;
altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled"; status = "disabled";
}; };

1
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
View File

@ -73,6 +73,7 @@
cap-sd-highspeed; cap-sd-highspeed;
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
}; };
&osc1 { &osc1 {

4
arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
View File

@ -16,11 +16,11 @@
partition@0 { partition@0 {
label = "Boot and fpga data"; label = "Boot and fpga data";
reg = <0x0 0x02000000>; reg = <0x0 0x02500000>;
}; };
partition@1c00000 { partition@1c00000 {
label = "Root Filesystem - JFFS2"; label = "Root Filesystem - JFFS2";
reg = <0x02000000 0x06000000>; reg = <0x02500000 0x05500000>;
}; };
}; };
}; };

1
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts
View File

@ -12,6 +12,7 @@
cap-mmc-highspeed; cap-mmc-highspeed;
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
}; };
&eccmgr { &eccmgr {

3
arch/arm/boot/dts/socfpga_arria5.dtsi
View File

@ -18,11 +18,12 @@
}; };
}; };
mmc0: dwmmc0@ff704000 { mmc0: mmc@ff704000 {
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
cap-mmc-highspeed; cap-mmc-highspeed;
cap-sd-highspeed; cap-sd-highspeed;
clk-phase-sd-hs = <0>, <135>;
}; };
sysmgr@ffd08000 { sysmgr@ffd08000 {

3
arch/arm/boot/dts/socfpga_cyclone5.dtsi
View File

@ -18,11 +18,12 @@
}; };
}; };
mmc0: dwmmc0@ff704000 { mmc0: mmc@ff704000 {
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
cap-mmc-highspeed; cap-mmc-highspeed;
cap-sd-highspeed; cap-sd-highspeed;
clk-phase-sd-hs = <0>, <135>;
}; };
sysmgr@ffd08000 { sysmgr@ffd08000 {

1
arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi
View File

@ -18,5 +18,6 @@
&mmc0 { /* On-SoM eMMC */ &mmc0 { /* On-SoM eMMC */
bus-width = <8>; bus-width = <8>;
clk-phase-sd-hs = <0>, <135>;
status = "okay"; status = "okay";
}; };

2
arch/arm/boot/dts/socfpga_vt.dts
View File

@ -29,7 +29,7 @@
}; };
}; };
dwmmc0@ff704000 { mmc@ff704000 {
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
cap-mmc-highspeed; cap-mmc-highspeed;

1
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -309,6 +309,7 @@
<&clkmgr STRATIX10_SDMMC_CLK>; <&clkmgr STRATIX10_SDMMC_CLK>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
iommus = <&smmu 5>; iommus = <&smmu 5>;
altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled"; status = "disabled";
}; };

1
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@ -105,6 +105,7 @@
cap-mmc-highspeed; cap-mmc-highspeed;
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
}; };
&osc1 { &osc1 {

1
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -313,6 +313,7 @@
<&clkmgr AGILEX_SDMMC_CLK>; <&clkmgr AGILEX_SDMMC_CLK>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
iommus = <&smmu 5>; iommus = <&smmu 5>;
altr,sysmgr-syscon = <&sysmgr 0x28 4>;
status = "disabled"; status = "disabled";
}; };

1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View File

@ -83,6 +83,7 @@
cap-sd-highspeed; cap-sd-highspeed;
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
}; };
&osc1 { &osc1 {

1
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
View File

@ -74,6 +74,7 @@
cap-sd-highspeed; cap-sd-highspeed;
broken-cd; broken-cd;
bus-width = <4>; bus-width = <4>;
clk-phase-sd-hs = <0>, <135>;
}; };
&osc1 { &osc1 {