From 869eee39b330f525c6280730d944074c8989f5d9 Mon Sep 17 00:00:00 2001 From: Prasad Malisetty Date: Tue, 16 Nov 2021 16:31:46 +0530 Subject: [PATCH] arm64: dts: qcom: sc7280: Fix incorrect clock name [ Upstream commit fa09b2248714c64644576d8064e9bd292a504a0e ] Replace pcie_1_pipe-clk clock name with pcie_1_pipe_clk To match with dt binding. Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node") Signed-off-by: Prasad Malisetty Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1637060508-30375-2-git-send-email-pmaliset@codeaurora.org Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f58336536a92..692973c4f434 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -429,7 +429,7 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>, <0>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", - "pcie_0_pipe_clk", "pcie_1_pipe-clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";