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drm/amd/display: add idle wait for passive surface update and modeset

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Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang
2017-07-23 15:18:57 -04:00
committed by Alex Deucher
parent 755d3bcfd4
commit 8748068764
7 changed files with 46 additions and 3 deletions
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2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
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@ -38,10 +38,8 @@
struct core_stream;
#define MAX_PIPES 6
#define MAX_CLOCK_SOURCES 7
/********* core_surface **********/
#define DC_SURFACE_TO_CORE(dc_surface) \
container_of(dc_surface, struct core_surface, public)

3
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
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@ -32,6 +32,9 @@
/******************************************************************************
* Data types shared between different Virtual HW blocks
******************************************************************************/
#define MAX_PIPES 6
struct gamma_curve {
uint32_t offset;
uint32_t segments_num;

1
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
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@ -207,6 +207,7 @@ struct output_pixel_processor {
struct dc_context *ctx;
uint32_t inst;
struct pwl_params regamma_params;
bool mpcc_disconnect_pending[MAX_PIPES];
const struct opp_funcs *funcs;
};

2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -156,6 +156,8 @@ struct hw_sequencer_funcs {
void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
void (*log_hw_state)(struct core_dc *dc);
void (*wait_for_mpcc_disconnect)(struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx);
};
void color_space_to_black_color(