iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

docs: arm64: booting.rst: get rid of some warnings

Browse Source 
Get rid of those warnings:

    Documentation/arm64/booting.rst:253: WARNING: Unexpected indentation.
    Documentation/arm64/booting.rst:259: WARNING: Block quote ends without a blank line; unexpected unindent.

By adding an extra blank lines where needed.

While here, use list markups on some places, as otherwise Sphinx
will consider the next lines as continuation of the privious ones.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/121b267be0a102fde73498c31792e5a9309013cc.1586881715.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
This commit is contained in:
Mauro Carvalho Chehab
2020-04-14 18:48:39 +02:00
committed by Jonathan Corbet
parent d91589556b
commit 877a37d31e
1 changed files with 22 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
Documentation/arm64/booting.rst
View File

@ -173,7 +173,9 @@ Before jumping into the kernel, the following conditions must be met:
- Caches, MMUs - Caches, MMUs
The MMU must be off. The MMU must be off.
Instruction cache may be on or off. Instruction cache may be on or off.
The address range corresponding to the loaded kernel image must be The address range corresponding to the loaded kernel image must be
cleaned to the PoC. In the presence of a system cache or other cleaned to the PoC. In the presence of a system cache or other
coherent masters with caches enabled, this will typically require coherent masters with caches enabled, this will typically require
@ -238,6 +240,7 @@ Before jumping into the kernel, the following conditions must be met:
- The DT or ACPI tables must describe a GICv2 interrupt controller. - The DT or ACPI tables must describe a GICv2 interrupt controller.
For CPUs with pointer authentication functionality: For CPUs with pointer authentication functionality:
- If EL3 is present: - If EL3 is present:
- SCR_EL3.APK (bit 16) must be initialised to 0b1 - SCR_EL3.APK (bit 16) must be initialised to 0b1
@ -249,18 +252,22 @@ Before jumping into the kernel, the following conditions must be met:
- HCR_EL2.API (bit 41) must be initialised to 0b1 - HCR_EL2.API (bit 41) must be initialised to 0b1
For CPUs with Activity Monitors Unit v1 (AMUv1) extension present: For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
- If EL3 is present: - If EL3 is present:
CPTR_EL3.TAM (bit 30) must be initialised to 0b0
CPTR_EL2.TAM (bit 30) must be initialised to 0b0 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
AMCNTENSET0_EL0 must be initialised to 0b1111 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
AMCNTENSET1_EL0 must be initialised to a platform specific value - AMCNTENSET0_EL0 must be initialised to 0b1111
having 0b1 set for the corresponding bit for each of the auxiliary - AMCNTENSET1_EL0 must be initialised to a platform specific value
counters present. having 0b1 set for the corresponding bit for each of the auxiliary
counters present.
- If the kernel is entered at EL1: - If the kernel is entered at EL1:
AMCNTENSET0_EL0 must be initialised to 0b1111
AMCNTENSET1_EL0 must be initialised to a platform specific value - AMCNTENSET0_EL0 must be initialised to 0b1111
having 0b1 set for the corresponding bit for each of the auxiliary - AMCNTENSET1_EL0 must be initialised to a platform specific value
counters present. having 0b1 set for the corresponding bit for each of the auxiliary
counters present.
The requirements described above for CPU mode, caches, MMUs, architected The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must timers, coherency and system registers apply to all CPUs. All CPUs must
@ -304,7 +311,8 @@ following manner:
Documentation/devicetree/bindings/arm/psci.yaml. Documentation/devicetree/bindings/arm/psci.yaml.
- Secondary CPU general-purpose register settings - Secondary CPU general-purpose register settings
x0 = 0 (reserved for future use)
x1 = 0 (reserved for future use) - x0 = 0 (reserved for future use)
x2 = 0 (reserved for future use) - x1 = 0 (reserved for future use)
x3 = 0 (reserved for future use) - x2 = 0 (reserved for future use)
- x3 = 0 (reserved for future use)