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drm/amdgpu: add gmc v9 supports for renoir

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Add gfx memory controller support for renoir.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2019-07-24 13:42:16 -05:00 committed by Alex Deucher
parent 080deab66d
commit 8787ee0145
1 changed files with 7 additions and 0 deletions
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7
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
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@ -703,6 +703,7 @@ static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_ARCTURUS: case CHIP_ARCTURUS:
case CHIP_RENOIR:
return true; return true;
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
@ -1009,6 +1010,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = 512ULL << 20; adev->gmc.gart_size = 512ULL << 20;
break; break;
case CHIP_RAVEN: /* DCE SG support */ case CHIP_RAVEN: /* DCE SG support */
case CHIP_RENOIR:
adev->gmc.gart_size = 1024ULL << 20; adev->gmc.gart_size = 1024ULL << 20;
break; break;
} }
@ -1059,6 +1061,7 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_RENOIR:
viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
size = (REG_GET_FIELD(viewport, size = (REG_GET_FIELD(viewport,
HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
@ -1115,8 +1118,10 @@ static int gmc_v9_0_sw_init(void *handle)
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RENOIR:
adev->num_vmhubs = 2; adev->num_vmhubs = 2;
/* /*
* To fulfill 4-level page support, * To fulfill 4-level page support,
* vm size is 256TB (48bit), maximum size of Vega10, * vm size is 256TB (48bit), maximum size of Vega10,
@ -1288,6 +1293,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA12: case CHIP_VEGA12:
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
/* TODO for renoir */
soc15_program_register_sequence(adev, soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0, golden_settings_athub_1_0_0,
ARRAY_SIZE(golden_settings_athub_1_0_0)); ARRAY_SIZE(golden_settings_athub_1_0_0));
@ -1322,6 +1328,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
/* TODO for renoir */
mmhub_v1_0_update_power_gating(adev, true); mmhub_v1_0_update_power_gating(adev, true);
break; break;
default: default: