iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fixup pagefault issue of mixer driver

Browse Source 
- it makes sure to check shadow register for interlace scan.
 - it corrects chroma_addr[1], height and vertical position values.
 And trivial cleanup
 - it just removes duplicated drm_bridge_attach.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJa8j7OAAoJEFc4NIkMQxK4s/8P/AgW0XmMYtKISiGDH9YIXrB/
 Y1i6Nyqbey/v5gLx5sKIAC4l0rfW06Lt1dcxRpN5T2iuwuMzClI8/NJ7RRje1QNM
 gAfTBtMQEayqaYtIIj2rBKE4ukuQE8wKGMKrlU9X4ccI/1a/Gc8plv4OJlYwOOtv
 ErqoZS40oRBwyt9EZX3MaFQriQh2zA/nGIcEbK0NPrkIBAy6bYEJEPmmnLAH7Vvs
 zzGyZX2i/6lRVlHx28PoO2TAuWT7laMVGOUJwR5lz57kQTE7Ua/k82ci1kpXUY5I
 F3jIUs83QqMiFT4+7sdKFuJ+X62Zs2SbXdtnvC0pA6d0/3wJKb8tGQ3yxKi5cuaD
 F6R6jCJcmldqFfsnmPDoL9ApyzSB7DfF8nynyVgkEkLDBfka4HXv4xI9q0mRj+/z
 v7qgw9hcO7yAKC+w56rn6jCz2QcUIqPDYlf+PAxUO8vNrJuGMo4SSimTMHSqJY/P
 3m/63BF+81GD4O+CIInq29PpAInvwCpKEL+TyFvnJIddltPEybyRCWS/HW18Uw/p
 n0kQKAfQ2rH+tj7IrcuJZ3ncfuWEZUQLQpqwHusrKUQP/JzOiDULC+lUMqXBt18x
 0nJcu6KOPX1eEPzpHz8RbShBKxz5epuODjVK88jr1PFO37CtHbGhyXrSd3YoMJaQ
 37FV0JlKUUPPhK+izHxK
 =aEUk
 -----END PGP SIGNATURE-----

Merge tag 'exynos-drm-fixes-for-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-fixes

Fixup pagefault issue of mixer driver
- it makes sure to check shadow register for interlace scan.
- it corrects chroma_addr[1], height and vertical position values.
And trivial cleanup
- it just removes duplicated drm_bridge_attach.

* tag 'exynos-drm-fixes-for-v4.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
  drm/exynos: hdmi: avoid duplicating drm_bridge_attach
  drm/exynos: mixer: avoid Oops in vp_video_buffer()
  drm/exynos/mixer: fix synchronization check in interlaced mode
This commit is contained in:
Dave Airlie 2018-05-10 11:27:04 +10:00
commit 87bf742b08
3 changed files with 18 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/exynos/exynos_hdmi.c
View File

@ -954,8 +954,6 @@ static int hdmi_create_connector(struct drm_encoder *encoder)
drm_mode_connector_attach_encoder(connector, encoder); drm_mode_connector_attach_encoder(connector, encoder);
if (hdata->bridge) { if (hdata->bridge) {
encoder->bridge = hdata->bridge;
hdata->bridge->encoder = encoder;
ret = drm_bridge_attach(encoder, hdata->bridge, NULL); ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
if (ret) if (ret)
DRM_ERROR("Failed to attach bridge\n"); DRM_ERROR("Failed to attach bridge\n");

22
drivers/gpu/drm/exynos/exynos_mixer.c
View File

@ -473,7 +473,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
chroma_addr[1] = chroma_addr[0] + 0x40; chroma_addr[1] = chroma_addr[0] + 0x40;
} else { } else {
luma_addr[1] = luma_addr[0] + fb->pitches[0]; luma_addr[1] = luma_addr[0] + fb->pitches[0];
chroma_addr[1] = chroma_addr[0] + fb->pitches[0]; chroma_addr[1] = chroma_addr[0] + fb->pitches[1];
} }
} else { } else {
luma_addr[1] = 0; luma_addr[1] = 0;
@ -482,6 +482,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
spin_lock_irqsave(&ctx->reg_slock, flags); spin_lock_irqsave(&ctx->reg_slock, flags);
vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
/* interlace or progressive scan mode */ /* interlace or progressive scan mode */
val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP); vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
@ -495,21 +496,23 @@ static void vp_video_buffer(struct mixer_context *ctx,
vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
VP_IMG_VSIZE(fb->height)); VP_IMG_VSIZE(fb->height));
/* chroma plane for NV12/NV21 is half the height of the luma plane */ /* chroma plane for NV12/NV21 is half the height of the luma plane */
vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
VP_IMG_VSIZE(fb->height / 2)); VP_IMG_VSIZE(fb->height / 2));
vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w); vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
vp_reg_write(ctx, VP_SRC_H_POSITION, vp_reg_write(ctx, VP_SRC_H_POSITION,
VP_SRC_H_POSITION_VAL(state->src.x)); VP_SRC_H_POSITION_VAL(state->src.x));
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w); vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x); vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2);
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2);
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2); vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2); vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
} else { } else {
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h); vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y); vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
} }
@ -699,6 +702,15 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
/* interlace scan need to check shadow register */ /* interlace scan need to check shadow register */
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
vp_reg_read(ctx, VP_SHADOW_UPDATE))
goto out;
base = mixer_reg_read(ctx, MXR_CFG);
shadow = mixer_reg_read(ctx, MXR_CFG_S);
if (base != shadow)
goto out;
base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0)); base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0)); shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
if (base != shadow) if (base != shadow)

1
drivers/gpu/drm/exynos/regs-mixer.h
View File

@ -47,6 +47,7 @@
#define MXR_MO 0x0304 #define MXR_MO 0x0304
#define MXR_RESOLUTION 0x0310 #define MXR_RESOLUTION 0x0310
#define MXR_CFG_S 0x2004
#define MXR_GRAPHIC0_BASE_S 0x2024 #define MXR_GRAPHIC0_BASE_S 0x2024
#define MXR_GRAPHIC1_BASE_S 0x2044 #define MXR_GRAPHIC1_BASE_S 0x2044