ARM: SoC fixes for 6.7, part 2
There are only a handful of bugfixes this time, which feels almost too small, so I hope we are not missing something important. - One more mediatek dts warning fix after the previous larger set, this should finally result in a clean defconfig build. - TI OMAP dts fixes for a spurious hang on am335x and invalid data on DTA7 - One DTS fix for ethernet on Oriange Pi Zero (Allwinner H616) - A regression fix for ti-sysc interconnect target module driver to not access registers after reset if srst_udelay quirk is needed - Reset controller driver fixes for a crash during error handling and a build warning -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWC6TcACgkQYKtH/8kJ UidYdw/9F+yGbp71bmlq+pqrqMflw1Xg921gTSx8t4H2PwDY9EID/4TEPQKRP7rj FV5r0wegJZMGnu9omCUOj2v71g6eT1S/Ces58u5dp57rcCV4cnUMXumcw/hxwXXE hb9l941EFpp/0ARcR8X0SK56xJQiGdsEdH9CD9IpX89CjEuQ3hAgPuw3EagBYsLX 9ncyv9ngkiaD5INNf3+bKAsHNL9AHDqGT8230RwHF9yOBoq53blSfGwN3ma9C3M/ lGF+24FgBByXRZWVWU8aWQuD9BMp8IADwYDY7qORUbBgEdlp87n7TkdVmqmC+io7 C+qRcwwWHy1vA8TKIU17ybicnCuI0/LSWj9OpDx63gKtw/YAyeR2GRH7VheJJT3G OOQDfUH2BbF74sqC+uRtP5K1Da1KjmIeSvyq0ClxqYAtvhXrsJjWm5fGvw13MPM0 gDK4DcD3iNpSJgj7+YQ4p5aQ9LPkX3TwLZilTPFVJzZXWY7+fa/NKi5ySAUUWZU2 vs3l072WkujAVv8OVrdeAyNEafhQG9vJDbya3dOTGdt416VIvmBAviqGI313D6u/ neoxOeRgu4ewa8qYYhRn7YK2pFZkKFVY9Lq4kfx3Ee636zWb0QIDXS0wcFVoFLty Lawcqx+Jy9V14VRzRhVnIMlBl8CRdlCLC5WU0BFFveFQsFpx+pU= =oPLt -----END PGP SIGNATURE----- Merge tag 'soc-fixes-6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "There are only a handful of bugfixes this time, which feels almost too small, so I hope we are not missing something important. - One more mediatek dts warning fix after the previous larger set, this should finally result in a clean defconfig build. - TI OMAP dts fixes for a spurious hang on am335x and invalid data on DTA7 - One DTS fix for ethernet on Oriange Pi Zero (Allwinner H616) - A regression fix for ti-sysc interconnect target module driver to not access registers after reset if srst_udelay quirk is needed - Reset controller driver fixes for a crash during error handling and a build warning" * tag 'soc-fixes-6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: mediatek: mt8395-genio-1200-evk: add interrupt-parent for mt6360 ARM: dts: Fix occasional boot hang for am3 usb reset: Fix crash when freeing non-existent optional resets ARM: OMAP2+: Fix null pointer dereference and memory leak in omap_soc_device_init ARM: dts: dra7: Fix DRA7 L3 NoC node register size bus: ti-sysc: Flush posted write only after srst_udelay reset: hisilicon: hi6220: fix Wvoid-pointer-to-enum-cast warning arm64: dts: allwinner: h616: update emac for Orange Pi Zero 3
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commit
87c71dd604
@ -359,6 +359,7 @@
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-delay-us = <2>;
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clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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@ -147,7 +147,7 @@
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l3-noc@44000000 {
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compatible = "ti,dra7-l3-noc";
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reg = <0x44000000 0x1000>,
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reg = <0x44000000 0x1000000>,
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<0x45000000 0x1000>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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@ -793,11 +793,16 @@ void __init omap_soc_device_init(void)
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soc_dev_attr->machine = soc_name;
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soc_dev_attr->family = omap_get_family();
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if (!soc_dev_attr->family) {
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kfree(soc_dev_attr);
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return;
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}
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soc_dev_attr->revision = soc_rev;
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soc_dev_attr->custom_attr_group = omap_soc_groups[0];
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->family);
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kfree(soc_dev_attr);
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return;
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}
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@ -68,10 +68,7 @@
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&emac0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ext_rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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allwinner,rx-delay-ps = <3100>;
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allwinner,tx-delay-ps = <700>;
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status = "okay";
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};
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@ -13,6 +13,9 @@
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};
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&emac0 {
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allwinner,rx-delay-ps = <3100>;
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allwinner,tx-delay-ps = <700>;
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phy-mode = "rgmii";
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phy-supply = <®_dcdce>;
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};
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@ -13,6 +13,8 @@
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};
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&emac0 {
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allwinner,tx-delay-ps = <700>;
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phy-mode = "rgmii-rxid";
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phy-supply = <®_dldo1>;
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};
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@ -238,6 +238,7 @@
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mt6360: pmic@34 {
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compatible = "mediatek,mt6360";
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reg = <0x34>;
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interrupt-parent = <&pio>;
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interrupts = <128 IRQ_TYPE_EDGE_FALLING>;
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interrupt-names = "IRQB";
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interrupt-controller;
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@ -2158,13 +2158,23 @@ static int sysc_reset(struct sysc *ddata)
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sysc_val = sysc_read_sysconfig(ddata);
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sysc_val |= sysc_mask;
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sysc_write(ddata, sysc_offset, sysc_val);
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/* Flush posted write */
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/*
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* Some devices need a delay before reading registers
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* after reset. Presumably a srst_udelay is not needed
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* for devices that use a rstctrl register reset.
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*/
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if (ddata->cfg.srst_udelay)
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fsleep(ddata->cfg.srst_udelay);
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/*
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* Flush posted write. For devices needing srst_udelay
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* this should trigger an interconnect error if the
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* srst_udelay value is needed but not configured.
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*/
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sysc_val = sysc_read_sysconfig(ddata);
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}
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if (ddata->cfg.srst_udelay)
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fsleep(ddata->cfg.srst_udelay);
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if (ddata->post_reset_quirk)
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ddata->post_reset_quirk(ddata);
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@ -807,6 +807,9 @@ static void __reset_control_put_internal(struct reset_control *rstc)
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{
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lockdep_assert_held(&reset_list_mutex);
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if (IS_ERR_OR_NULL(rstc))
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return;
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kref_put(&rstc->refcnt, __reset_control_release);
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}
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@ -1017,11 +1020,8 @@ EXPORT_SYMBOL_GPL(reset_control_put);
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void reset_control_bulk_put(int num_rstcs, struct reset_control_bulk_data *rstcs)
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{
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mutex_lock(&reset_list_mutex);
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while (num_rstcs--) {
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if (IS_ERR_OR_NULL(rstcs[num_rstcs].rstc))
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continue;
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while (num_rstcs--)
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__reset_control_put_internal(rstcs[num_rstcs].rstc);
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}
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mutex_unlock(&reset_list_mutex);
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}
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EXPORT_SYMBOL_GPL(reset_control_bulk_put);
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@ -163,7 +163,7 @@ static int hi6220_reset_probe(struct platform_device *pdev)
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if (!data)
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return -ENOMEM;
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type = (enum hi6220_reset_ctrl_type)of_device_get_match_data(dev);
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type = (uintptr_t)of_device_get_match_data(dev);
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regmap = syscon_node_to_regmap(np);
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if (IS_ERR(regmap)) {
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