soc: mediatek: pm-domains: Add support for mt8186
Add power domain control data in mt8186. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Chun-Jie Chen
Matthias Brugger
parent
c8a006896f
commit
88590cbc17
344
drivers/soc/mediatek/mt8186-pm-domains.h
Normal file
344
drivers/soc/mediatek/mt8186-pm-domains.h
Normal file
@ -0,0 +1,344 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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*/
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#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8186-power.h>
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/*
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* MT8186 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
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[MT8186_POWER_DOMAIN_MFG0] = {
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.name = "mfg0",
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.sta_mask = BIT(2),
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.ctl_offs = 0x308,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8186_POWER_DOMAIN_MFG1] = {
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.name = "mfg1",
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.sta_mask = BIT(3),
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.ctl_offs = 0x30c,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_MFG2] = {
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.name = "mfg2",
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.sta_mask = BIT(4),
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.ctl_offs = 0x310,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_MFG3] = {
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.name = "mfg3",
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.sta_mask = BIT(5),
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.ctl_offs = 0x314,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_SSUSB] = {
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.name = "ssusb",
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.sta_mask = BIT(20),
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.ctl_offs = 0x9F0,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8186_POWER_DOMAIN_SSUSB_P1] = {
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.name = "ssusb_p1",
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.sta_mask = BIT(19),
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.ctl_offs = 0x9F4,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8186_POWER_DOMAIN_DIS] = {
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.name = "dis",
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.sta_mask = BIT(21),
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.ctl_offs = 0x354,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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},
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},
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[MT8186_POWER_DOMAIN_IMG] = {
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.name = "img",
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.sta_mask = BIT(13),
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.ctl_offs = 0x334,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_IMG2] = {
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.name = "img2",
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.sta_mask = BIT(14),
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.ctl_offs = 0x338,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_IPE] = {
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.name = "ipe",
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.sta_mask = BIT(15),
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.ctl_offs = 0x33C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM] = {
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.name = "cam",
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.sta_mask = BIT(23),
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.ctl_offs = 0x35C,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM_RAWA] = {
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.name = "cam_rawa",
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.sta_mask = BIT(24),
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.ctl_offs = 0x360,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CAM_RAWB] = {
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.name = "cam_rawb",
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.sta_mask = BIT(25),
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.ctl_offs = 0x364,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = BIT(18),
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.ctl_offs = 0x348,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = BIT(16),
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.ctl_offs = 0x340,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_WPE] = {
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.name = "wpe",
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.sta_mask = BIT(0),
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.ctl_offs = 0x3F8,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
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MT8186_TOP_AXI_PROT_EN_2_SET,
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MT8186_TOP_AXI_PROT_EN_2_CLR,
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MT8186_TOP_AXI_PROT_EN_2_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
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MT8186_TOP_AXI_PROT_EN_2_SET,
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MT8186_TOP_AXI_PROT_EN_2_CLR,
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MT8186_TOP_AXI_PROT_EN_2_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_CONN_ON] = {
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.name = "conn_on",
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.sta_mask = BIT(1),
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.ctl_offs = 0x304,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
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MT8186_TOP_AXI_PROT_EN_1_SET,
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MT8186_TOP_AXI_PROT_EN_1_CLR,
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MT8186_TOP_AXI_PROT_EN_1_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
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MT8186_TOP_AXI_PROT_EN_SET,
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MT8186_TOP_AXI_PROT_EN_CLR,
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MT8186_TOP_AXI_PROT_EN_STA),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8186_POWER_DOMAIN_CSIRX_TOP] = {
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.name = "csirx_top",
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.sta_mask = BIT(6),
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.ctl_offs = 0x318,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_ADSP_AO] = {
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.name = "adsp_ao",
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.sta_mask = BIT(17),
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.ctl_offs = 0x9FC,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_ADSP_INFRA] = {
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.name = "adsp_infra",
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.sta_mask = BIT(10),
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.ctl_offs = 0x9F8,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8186_POWER_DOMAIN_ADSP_TOP] = {
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.name = "adsp_top",
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.sta_mask = BIT(31),
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.ctl_offs = 0x3E4,
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.pwr_sta_offs = 0x16C,
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.pwr_sta2nd_offs = 0x170,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
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MT8186_TOP_AXI_PROT_EN_3_SET,
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MT8186_TOP_AXI_PROT_EN_3_CLR,
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MT8186_TOP_AXI_PROT_EN_3_STA),
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BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
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MT8186_TOP_AXI_PROT_EN_3_SET,
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MT8186_TOP_AXI_PROT_EN_3_CLR,
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MT8186_TOP_AXI_PROT_EN_3_STA),
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},
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.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
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},
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};
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static const struct scpsys_soc_data mt8186_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8186,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),
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};
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#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */
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@ -19,6 +19,7 @@
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#include "mt8167-pm-domains.h"
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#include "mt8173-pm-domains.h"
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#include "mt8183-pm-domains.h"
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#include "mt8186-pm-domains.h"
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#include "mt8192-pm-domains.h"
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#include "mt8195-pm-domains.h"
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@ -566,6 +567,10 @@ static const struct of_device_id scpsys_of_match[] = {
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.compatible = "mediatek,mt8183-power-controller",
|
||||
.data = &mt8183_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8186-power-controller",
|
||||
.data = &mt8186_scpsys_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8192-power-controller",
|
||||
.data = &mt8192_scpsys_data,
|
||||
|
||||
@ -140,6 +140,54 @@
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
|
||||
|
||||
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
|
||||
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
|
||||
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
|
||||
|
||||
/* MFG1 */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
|
||||
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
|
||||
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
|
||||
/* DIS */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
|
||||
#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
|
||||
/* IMG */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
|
||||
/* IPE */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
|
||||
/* CAM */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
|
||||
/* VENC */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
|
||||
/* VDEC */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
|
||||
/* WPE */
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
|
||||
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
|
||||
/* CONN_ON */
|
||||
#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
|
||||
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
|
||||
/* ADSP_TOP */
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
|
||||
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
|
||||
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
|
||||
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user