iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge series "ASoC: mediatek: Add support for MT8195 SoC" from Trevor Wu <trevor.wu@mediatek.com>:

Browse Source 
This series of patches adds support for Mediatek AFE of MT8195 SoC.
Patches are based on broonie tree "for-next" branch.

Changes since v4:
  - removed sof related code

Changes since v3:
  - fixed warnings found by kernel test robot
  - removed unused critical section
  - corrected the lock protected sections on etdm driver
  - added DPTX and HDMITX audio support

Changes since v2:
  - added audio clock gate control
  - added 'mediatek' prefix to private dts properties
  - added consumed clocks to dt-bindins and adopted suggestions from Rob
  - refined clock usage and remove unused clock and control code
  - fixed typos

Changes since v1:
  - fixed some problems related to dt-bindings
  - added some missing properties to dt-bindings
  - added depency declaration on dt-bindings
  - fixed some warnings found by kernel test robot

Trevor Wu (11):
  ASoC: mediatek: mt8195: update mediatek common driver
  ASoC: mediatek: mt8195: support audsys clock control
  ASoC: mediatek: mt8195: support etdm in platform driver
  ASoC: mediatek: mt8195: support adda in platform driver
  ASoC: mediatek: mt8195: support pcm in platform driver
  ASoC: mediatek: mt8195: add platform driver
  dt-bindings: mediatek: mt8195: add audio afe document
  ASoC: mediatek: mt8195: add machine driver with mt6359, rt1019 and
    rt5682
  ASoC: mediatek: mt8195: add DPTX audio support
  ASoC: mediatek: mt8195: add HDMITX audio support
  dt-bindings: mediatek: mt8195: add mt8195-mt6359-rt1019-rt5682
    document

 .../bindings/sound/mt8195-afe-pcm.yaml        |  184 +
 .../sound/mt8195-mt6359-rt1019-rt5682.yaml    |   47 +
 sound/soc/mediatek/Kconfig                    |   24 +
 sound/soc/mediatek/Makefile                   |    1 +
 sound/soc/mediatek/common/mtk-afe-fe-dai.c    |   22 +-
 sound/soc/mediatek/common/mtk-base-afe.h      |   10 +-
 sound/soc/mediatek/mt8195/Makefile            |   15 +
 sound/soc/mediatek/mt8195/mt8195-afe-clk.c    |  441 +++
 sound/soc/mediatek/mt8195/mt8195-afe-clk.h    |  109 +
 sound/soc/mediatek/mt8195/mt8195-afe-common.h |  158 +
 sound/soc/mediatek/mt8195/mt8195-afe-pcm.c    | 3281 +++++++++++++++++
 sound/soc/mediatek/mt8195/mt8195-audsys-clk.c |  214 ++
 sound/soc/mediatek/mt8195/mt8195-audsys-clk.h |   15 +
 .../soc/mediatek/mt8195/mt8195-audsys-clkid.h |   93 +
 sound/soc/mediatek/mt8195/mt8195-dai-adda.c   |  830 +++++
 sound/soc/mediatek/mt8195/mt8195-dai-etdm.c   | 2639 +++++++++++++
 sound/soc/mediatek/mt8195/mt8195-dai-pcm.c    |  389 ++
 .../mt8195/mt8195-mt6359-rt1019-rt5682.c      | 1087 ++++++
 sound/soc/mediatek/mt8195/mt8195-reg.h        | 2796 ++++++++++++++
 19 files changed, 12350 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml
 create mode 100644 Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1019-rt5682.yaml
 create mode 100644 sound/soc/mediatek/mt8195/Makefile
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-clk.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-clk.h
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-common.h
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-afe-pcm.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-audsys-clk.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-audsys-clk.h
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-audsys-clkid.h
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-dai-adda.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-dai-etdm.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-dai-pcm.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-mt6359-rt1019-rt5682.c
 create mode 100644 sound/soc/mediatek/mt8195/mt8195-reg.h

--
2.18.0
This commit is contained in:
Mark Brown 2021-08-25 10:50:21 +01:00
commit 88939e7375
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
19 changed files with 12350 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

184
Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml Normal file
View File

@ -0,0 +1,184 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek AFE PCM controller for mt8195
maintainers:
- Trevor Wu <trevor.wu@mediatek.com>
properties:
compatible:
const: mediatek,mt8195-audio
reg:
maxItems: 1
interrupts:
maxItems: 1
mediatek,topckgen:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of the mediatek topckgen controller
power-domains:
maxItems: 1
clocks:
items:
- description: 26M clock
- description: audio pll1 clock
- description: audio pll2 clock
- description: clock divider for i2si1_mck
- description: clock divider for i2si2_mck
- description: clock divider for i2so1_mck
- description: clock divider for i2so2_mck
- description: clock divider for dptx_mck
- description: a1sys hoping clock
- description: audio intbus clock
- description: audio hires clock
- description: audio local bus clock
- description: mux for dptx_mck
- description: mux for i2so1_mck
- description: mux for i2so2_mck
- description: mux for i2si1_mck
- description: mux for i2si2_mck
- description: audio infra 26M clock
- description: infra bus clock
clock-names:
items:
- const: clk26m
- const: apll1_ck
- const: apll2_ck
- const: apll12_div0
- const: apll12_div1
- const: apll12_div2
- const: apll12_div3
- const: apll12_div9
- const: a1sys_hp_sel
- const: aud_intbus_sel
- const: audio_h_sel
- const: audio_local_bus_sel
- const: dptx_m_sel
- const: i2so1_m_sel
- const: i2so2_m_sel
- const: i2si1_m_sel
- const: i2si2_m_sel
- const: infra_ao_audio_26m_b
- const: scp_adsp_audiodsp
mediatek,etdm-in1-chn-disabled:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 24
description: Specify which input channel should be disabled.
mediatek,etdm-in2-chn-disabled:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 16
description: Specify which input channel should be disabled.
patternProperties:
"^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
description: Specify etdm in mclk output rate for always on case.
"^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
description: Specify etdm out mclk output rate for always on case.
"^mediatek,etdm-in[1-2]-multi-pin-mode$":
type: boolean
description: if present, the etdm data mode is I2S.
"^mediatek,etdm-out[1-3]-multi-pin-mode$":
type: boolean
description: if present, the etdm data mode is I2S.
"^mediatek,etdm-in[1-2]-cowork-source$":
$ref: /schemas/types.yaml#/definitions/uint32
description: |
etdm modules can share the same external clock pin. Specify
which etdm clock source is required by this etdm in moudule.
enum:
- 0 # etdm1_in
- 1 # etdm2_in
- 2 # etdm1_out
- 3 # etdm2_out
"^mediatek,etdm-out[1-2]-cowork-source$":
$ref: /schemas/types.yaml#/definitions/uint32
description: |
etdm modules can share the same external clock pin. Specify
which etdm clock source is required by this etdm out moudule.
enum:
- 0 # etdm1_in
- 1 # etdm2_in
- 2 # etdm1_out
- 3 # etdm2_out
required:
- compatible
- reg
- interrupts
- mediatek,topckgen
- power-domains
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
afe: mt8195-afe-pcm@10890000 {
compatible = "mediatek,mt8195-audio";
reg = <0x10890000 0x10000>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_APLL1>,
<&topckgen CLK_TOP_APLL2>,
<&topckgen CLK_TOP_APLL12_DIV0>,
<&topckgen CLK_TOP_APLL12_DIV1>,
<&topckgen CLK_TOP_APLL12_DIV2>,
<&topckgen CLK_TOP_APLL12_DIV3>,
<&topckgen CLK_TOP_APLL12_DIV9>,
<&topckgen CLK_TOP_A1SYS_HP_SEL>,
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen CLK_TOP_AUDIO_H_SEL>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
<&topckgen CLK_TOP_DPTX_M_SEL>,
<&topckgen CLK_TOP_I2SO1_M_SEL>,
<&topckgen CLK_TOP_I2SO2_M_SEL>,
<&topckgen CLK_TOP_I2SI1_M_SEL>,
<&topckgen CLK_TOP_I2SI2_M_SEL>,
<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
<&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
clock-names = "clk26m",
"apll1_ck",
"apll2_ck",
"apll12_div0",
"apll12_div1",
"apll12_div2",
"apll12_div3",
"apll12_div9",
"a1sys_hp_sel",
"aud_intbus_sel",
"audio_h_sel",
"audio_local_bus_sel",
"dptx_m_sel",
"i2so1_m_sel",
"i2so2_m_sel",
"i2si1_m_sel",
"i2si2_m_sel",
"infra_ao_audio_26m_b",
"scp_adsp_audiodsp";
};
...

47
Documentation/devicetree/bindings/sound/mt8195-mt6359-rt1019-rt5682.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mt8195-mt6359-rt1019-rt5682.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8195 with MT6359, RT1019 and RT5682 ASoC sound card driver
maintainers:
- Trevor Wu <trevor.wu@mediatek.com>
description:
This binding describes the MT8195 sound card.
properties:
compatible:
const: mediatek,mt8195_mt6359_rt1019_rt5682
mediatek,platform:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 ASoC platform.
mediatek,dptx-codec:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 Display Port Tx codec node.
mediatek,hdmi-codec:
$ref: "/schemas/types.yaml#/definitions/phandle"
description: The phandle of MT8195 HDMI codec node.
additionalProperties: false
required:
- compatible
- mediatek,platform
examples:
- |
sound: mt8195-sound {
compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
mediatek,platform = <&afe>;
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
};
...

24
sound/soc/mediatek/Kconfig
View File

@ -184,3 +184,27 @@ config SND_SOC_MT8192_MT6359_RT1015_RT5682
with the MT6359 RT1015 RT5682 audio codec.
Select Y if you have such device.
If unsure select "N".
config SND_SOC_MT8195
tristate "ASoC support for Mediatek MT8195 chip"
select SND_SOC_MEDIATEK
help
This adds ASoC platform driver support for Mediatek MT8195 chip
that can be used with other codecs.
Select Y if you have such device.
If unsure select "N".
config SND_SOC_MT8195_MT6359_RT1019_RT5682
tristate "ASoC Audio driver for MT8195 with MT6359 RT1019 RT5682 codec"
depends on I2C
depends on SND_SOC_MT8195
select SND_SOC_MT6359
select SND_SOC_RT1015P
select SND_SOC_RT5682_I2C
select SND_SOC_DMIC
select SND_SOC_HDMI_CODEC
help
This adds ASoC driver for Mediatek MT8195 boards
with the MT6359 RT1019 RT5682 audio codec.
Select Y if you have such device.
If unsure select "N".

1
sound/soc/mediatek/Makefile
View File

@ -5,3 +5,4 @@ obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
obj-$(CONFIG_SND_SOC_MT8192) += mt8192/
obj-$(CONFIG_SND_SOC_MT8195) += mt8195/

22
sound/soc/mediatek/common/mtk-afe-fe-dai.c
View File

@ -139,7 +139,7 @@ int mtk_afe_fe_hw_params(struct snd_pcm_substream *substream,
substream->runtime->dma_area,
substream->runtime->dma_bytes);
memset_io(substream->runtime->dma_area, 0,
memset_io((void __force __iomem *)substream->runtime->dma_area, 0,
substream->runtime->dma_bytes);
/* set addr */
@ -433,11 +433,20 @@ int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
phys_buf_addr_upper_32);
}
/* set MSB to 33-bit */
if (memif->data->msb_reg >= 0)
/*
* set MSB to 33-bit, for memif address
* only for memif base address, if msb_end_reg exists
*/
if (memif->data->msb_reg)
mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
1, msb_at_bit33, memif->data->msb_shift);
/* set MSB to 33-bit, for memif end address */
if (memif->data->msb_end_reg)
mtk_regmap_update_bits(afe->regmap, memif->data->msb_end_reg,
1, msb_at_bit33,
memif->data->msb_end_shift);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
@ -464,6 +473,13 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe,
else
mono = (channel == 1) ? 1 : 0;
/* for specific configuration of memif mono mode */
if (memif->data->int_odd_flag_reg)
mtk_regmap_update_bits(afe->regmap,
memif->data->int_odd_flag_reg,
1, mono,
memif->data->int_odd_flag_shift);
return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
1, mono, memif->data->mono_shift);
}

10
sound/soc/mediatek/common/mtk-base-afe.h
View File

@ -29,6 +29,8 @@ struct mtk_base_memif_data {
int quad_ch_reg;
int quad_ch_mask;
int quad_ch_shift;
int int_odd_flag_reg;
int int_odd_flag_shift;
int enable_reg;
int enable_shift;
int hd_reg;
@ -37,10 +39,13 @@ struct mtk_base_memif_data {
int hd_align_mshift;
int msb_reg;
int msb_shift;
int msb2_reg;
int msb2_shift;
int msb_end_reg;
int msb_end_shift;
int agent_disable_reg;
int agent_disable_shift;
int ch_num_reg;
int ch_num_shift;
int ch_num_maskbit;
/* playback memif only */
int pbuf_reg;
int pbuf_mask;
@ -62,6 +67,7 @@ struct mtk_base_irq_data {
int irq_en_shift;
int irq_clr_reg;
int irq_clr_shift;
int irq_status_shift;
};
struct device;

15
sound/soc/mediatek/mt8195/Makefile Normal file
View File

@ -0,0 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
# platform driver
snd-soc-mt8195-afe-objs := \
mt8195-audsys-clk.o \
mt8195-afe-clk.o \
mt8195-afe-pcm.o \
mt8195-dai-adda.o \
mt8195-dai-etdm.o \
mt8195-dai-pcm.o
obj-$(CONFIG_SND_SOC_MT8195) += snd-soc-mt8195-afe.o
# machine driver
obj-$(CONFIG_SND_SOC_MT8195_MT6359_RT1019_RT5682) += mt8195-mt6359-rt1019-rt5682.o

441
sound/soc/mediatek/mt8195/mt8195-afe-clk.c Normal file
View File

@ -0,0 +1,441 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
* Trevor Wu <trevor.wu@mediatek.com>
*/
#include <linux/clk.h>
#include "mt8195-afe-common.h"
#include "mt8195-afe-clk.h"
#include "mt8195-reg.h"
#include "mt8195-audsys-clk.h"
static const char *aud_clks[MT8195_CLK_NUM] = {
/* xtal */
[MT8195_CLK_XTAL_26M] = "clk26m",
/* divider */
[MT8195_CLK_TOP_APLL1] = "apll1_ck",
[MT8195_CLK_TOP_APLL2] = "apll2_ck",
[MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
[MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
[MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
[MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
[MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
/* mux */
[MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
[MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
[MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
[MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
[MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
[MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
[MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
[MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
[MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
/* clock gate */
[MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
[MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
/* afe clock gate */
[MT8195_CLK_AUD_AFE] = "aud_afe",
[MT8195_CLK_AUD_APLL] = "aud_apll",
[MT8195_CLK_AUD_APLL2] = "aud_apll2",
[MT8195_CLK_AUD_DAC] = "aud_dac",
[MT8195_CLK_AUD_ADC] = "aud_adc",
[MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
[MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
[MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
[MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
[MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
[MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
[MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
[MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
[MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
[MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
[MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
[MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
[MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
[MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
[MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
[MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
[MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
[MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
[MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
[MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
[MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
[MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
[MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
[MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
[MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
[MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
[MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
[MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
[MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
[MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
[MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
};
int mt8195_afe_get_mclk_source_clk_id(int sel)
{
switch (sel) {
case MT8195_MCK_SEL_26M:
return MT8195_CLK_XTAL_26M;
case MT8195_MCK_SEL_APLL1:
return MT8195_CLK_TOP_APLL1;
case MT8195_MCK_SEL_APLL2:
return MT8195_CLK_TOP_APLL2;
default:
return -EINVAL;
}
}
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
if (clk_id < 0) {
dev_dbg(afe->dev, "invalid clk id\n");
return 0;
}
return clk_get_rate(afe_priv->clk[clk_id]);
}
int mt8195_afe_get_default_mclk_source_by_rate(int rate)
{
return ((rate % 8000) == 0) ?
MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
}
int mt8195_afe_init_clock(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
mt8195_audsys_clk_register(afe);
afe_priv->clk =
devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
GFP_KERNEL);
if (!afe_priv->clk)
return -ENOMEM;
for (i = 0; i < MT8195_CLK_NUM; i++) {
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
if (IS_ERR(afe_priv->clk[i])) {
dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
__func__, aud_clks[i],
PTR_ERR(afe_priv->clk[i]));
return PTR_ERR(afe_priv->clk[i]);
}
}
return 0;
}
void mt8195_afe_deinit_clock(struct mtk_base_afe *afe)
{
mt8195_audsys_clk_unregister(afe);
}
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_prepare_enable(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to enable clk\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_disable_unprepare(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_prepare(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_unprepare(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{
int ret;
if (clk) {
ret = clk_enable(clk);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to clk enable\n",
__func__);
return ret;
}
} else {
dev_dbg(afe->dev, "NULL clk\n");
}
return 0;
}
void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
{
if (clk)
clk_disable(clk);
else
dev_dbg(afe->dev, "NULL clk\n");
}
int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
unsigned int rate)
{
int ret;
if (clk) {
ret = clk_set_rate(clk, rate);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
__func__);
return ret;
}
}
return 0;
}
int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
struct clk *parent)
{
int ret;
if (clk && parent) {
ret = clk_set_parent(clk, parent);
if (ret) {
dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
__func__);
return ret;
}
}
return 0;
}
static unsigned int get_top_cg_reg(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return ASYS_TOP_CON;
default:
return 0;
}
}
static unsigned int get_top_cg_mask(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
return ASYS_TOP_CON_A1SYS_TIMING_ON;
case MT8195_TOP_CG_A2SYS_TIMING:
return ASYS_TOP_CON_A2SYS_TIMING_ON;
case MT8195_TOP_CG_26M_TIMING:
return ASYS_TOP_CON_26M_TIMING_ON;
default:
return 0;
}
}
static unsigned int get_top_cg_on_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return get_top_cg_mask(cg_type);
default:
return 0;
}
}
static unsigned int get_top_cg_off_val(unsigned int cg_type)
{
switch (cg_type) {
case MT8195_TOP_CG_A1SYS_TIMING:
case MT8195_TOP_CG_A2SYS_TIMING:
case MT8195_TOP_CG_26M_TIMING:
return 0;
default:
return get_top_cg_mask(cg_type);
}
}
static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_on_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
{
unsigned int reg = get_top_cg_reg(cg_type);
unsigned int mask = get_top_cg_mask(cg_type);
unsigned int val = get_top_cg_off_val(cg_type);
regmap_update_bits(afe->regmap, reg, mask, val);
return 0;
}
int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
unsigned int clk_array[] = {
MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
MT8195_CLK_AUD_AFE, /* AFE HW master switch */
MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
unsigned int clk_array[] = {
MT8195_CLK_AUD_A1SYS,
MT8195_CLK_AUD_A1SYS_HP,
MT8195_CLK_AUD_AFE,
MT8195_CLK_INFRA_AO_AUDIO_26M_B,
MT8195_CLK_TOP_AUD_INTBUS_SEL,
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
MT8195_CLK_TOP_AUDIO_H_SEL,
MT8195_CLK_SCP_ADSP_AUDIODSP,
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
return 0;
}
static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
return 0;
}
static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
unsigned int clk_array[] = {
MT8195_CLK_AUD_A1SYS,
MT8195_CLK_AUD_A2SYS,
};
unsigned int cg_array[] = {
MT8195_TOP_CG_A1SYS_TIMING,
MT8195_TOP_CG_A2SYS_TIMING,
MT8195_TOP_CG_26M_TIMING,
};
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
mt8195_afe_enable_top_cg(afe, cg_array[i]);
return 0;
}
static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int i;
unsigned int clk_array[] = {
MT8195_CLK_AUD_A2SYS,
MT8195_CLK_AUD_A1SYS,
};
unsigned int cg_array[] = {
MT8195_TOP_CG_26M_TIMING,
MT8195_TOP_CG_A2SYS_TIMING,
MT8195_TOP_CG_A1SYS_TIMING,
};
for (i = 0; i < ARRAY_SIZE(cg_array); i++)
mt8195_afe_disable_top_cg(afe, cg_array[i]);
for (i = 0; i < ARRAY_SIZE(clk_array); i++)
mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
return 0;
}
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
{
mt8195_afe_enable_timing_sys(afe);
mt8195_afe_enable_afe_on(afe);
return 0;
}
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
{
mt8195_afe_disable_afe_on(afe);
mt8195_afe_disable_timing_sys(afe);
return 0;
}

109
sound/soc/mediatek/mt8195/mt8195-afe-clk.h Normal file
View File

@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
* Trevor Wu <trevor.wu@mediatek.com>
*/
#ifndef _MT8195_AFE_CLK_H_
#define _MT8195_AFE_CLK_H_
enum {
/* xtal */
MT8195_CLK_XTAL_26M,
/* divider */
MT8195_CLK_TOP_APLL1,
MT8195_CLK_TOP_APLL2,
MT8195_CLK_TOP_APLL12_DIV0,
MT8195_CLK_TOP_APLL12_DIV1,
MT8195_CLK_TOP_APLL12_DIV2,
MT8195_CLK_TOP_APLL12_DIV3,
MT8195_CLK_TOP_APLL12_DIV9,
/* mux */
MT8195_CLK_TOP_A1SYS_HP_SEL,
MT8195_CLK_TOP_AUD_INTBUS_SEL,
MT8195_CLK_TOP_AUDIO_H_SEL,
MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
MT8195_CLK_TOP_DPTX_M_SEL,
MT8195_CLK_TOP_I2SO1_M_SEL,
MT8195_CLK_TOP_I2SO2_M_SEL,
MT8195_CLK_TOP_I2SI1_M_SEL,
MT8195_CLK_TOP_I2SI2_M_SEL,
/* clock gate */
MT8195_CLK_INFRA_AO_AUDIO_26M_B,
MT8195_CLK_SCP_ADSP_AUDIODSP,
MT8195_CLK_AUD_AFE,
MT8195_CLK_AUD_APLL,
MT8195_CLK_AUD_APLL2,
MT8195_CLK_AUD_DAC,
MT8195_CLK_AUD_ADC,
MT8195_CLK_AUD_DAC_HIRES,
MT8195_CLK_AUD_A1SYS_HP,
MT8195_CLK_AUD_ADC_HIRES,
MT8195_CLK_AUD_ADDA6_ADC,
MT8195_CLK_AUD_ADDA6_ADC_HIRES,
MT8195_CLK_AUD_I2SIN,
MT8195_CLK_AUD_TDM_IN,
MT8195_CLK_AUD_I2S_OUT,
MT8195_CLK_AUD_TDM_OUT,
MT8195_CLK_AUD_HDMI_OUT,
MT8195_CLK_AUD_ASRC11,
MT8195_CLK_AUD_ASRC12,
MT8195_CLK_AUD_A1SYS,
MT8195_CLK_AUD_A2SYS,
MT8195_CLK_AUD_PCMIF,
MT8195_CLK_AUD_MEMIF_UL1,
MT8195_CLK_AUD_MEMIF_UL2,
MT8195_CLK_AUD_MEMIF_UL3,
MT8195_CLK_AUD_MEMIF_UL4,
MT8195_CLK_AUD_MEMIF_UL5,
MT8195_CLK_AUD_MEMIF_UL6,
MT8195_CLK_AUD_MEMIF_UL8,
MT8195_CLK_AUD_MEMIF_UL9,
MT8195_CLK_AUD_MEMIF_UL10,
MT8195_CLK_AUD_MEMIF_DL2,
MT8195_CLK_AUD_MEMIF_DL3,
MT8195_CLK_AUD_MEMIF_DL6,
MT8195_CLK_AUD_MEMIF_DL7,
MT8195_CLK_AUD_MEMIF_DL8,
MT8195_CLK_AUD_MEMIF_DL10,
MT8195_CLK_AUD_MEMIF_DL11,
MT8195_CLK_NUM,
};
enum {
MT8195_MCK_SEL_26M,
MT8195_MCK_SEL_APLL1,
MT8195_MCK_SEL_APLL2,
MT8195_MCK_SEL_APLL3,
MT8195_MCK_SEL_APLL4,
MT8195_MCK_SEL_APLL5,
MT8195_MCK_SEL_HDMIRX_APLL,
MT8195_MCK_SEL_NUM,
};
struct mtk_base_afe;
int mt8195_afe_get_mclk_source_clk_id(int sel);
int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll);
int mt8195_afe_get_default_mclk_source_by_rate(int rate);
int mt8195_afe_init_clock(struct mtk_base_afe *afe);
void mt8195_afe_deinit_clock(struct mtk_base_afe *afe);
int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
unsigned int rate);
int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
struct clk *parent);
int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe);
int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe);
int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
#endif

158
sound/soc/mediatek/mt8195/mt8195-afe-common.h Normal file
View File

@ -0,0 +1,158 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mt8195-afe-common.h -- Mediatek 8195 audio driver definitions
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
* Trevor Wu <trevor.wu@mediatek.com>
*/
#ifndef _MT_8195_AFE_COMMON_H_
#define _MT_8195_AFE_COMMON_H_
#include <sound/soc.h>
#include <linux/list.h>
#include <linux/regmap.h>
#include "../common/mtk-base-afe.h"
enum {
MT8195_DAI_START,
MT8195_AFE_MEMIF_START = MT8195_DAI_START,
MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START,
MT8195_AFE_MEMIF_DL3,
MT8195_AFE_MEMIF_DL6,
MT8195_AFE_MEMIF_DL7,
MT8195_AFE_MEMIF_DL8,
MT8195_AFE_MEMIF_DL10,
MT8195_AFE_MEMIF_DL11,
MT8195_AFE_MEMIF_UL_START,
MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START,
MT8195_AFE_MEMIF_UL2,
MT8195_AFE_MEMIF_UL3,
MT8195_AFE_MEMIF_UL4,
MT8195_AFE_MEMIF_UL5,
MT8195_AFE_MEMIF_UL6,
MT8195_AFE_MEMIF_UL8,
MT8195_AFE_MEMIF_UL9,
MT8195_AFE_MEMIF_UL10,
MT8195_AFE_MEMIF_END,
MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START),
MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END,
MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START,
MT8195_AFE_IO_DPTX,
MT8195_AFE_IO_ETDM_START,
MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START,
MT8195_AFE_IO_ETDM2_IN,
MT8195_AFE_IO_ETDM1_OUT,
MT8195_AFE_IO_ETDM2_OUT,
MT8195_AFE_IO_ETDM3_OUT,
MT8195_AFE_IO_ETDM_END,
MT8195_AFE_IO_ETDM_NUM =
(MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START),
MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END,
MT8195_AFE_IO_UL_SRC1,
MT8195_AFE_IO_UL_SRC2,
MT8195_AFE_IO_END,
MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START),
MT8195_DAI_END = MT8195_AFE_IO_END,
MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START),
};
enum {
MT8195_TOP_CG_A1SYS_TIMING,
MT8195_TOP_CG_A2SYS_TIMING,
MT8195_TOP_CG_26M_TIMING,
MT8195_TOP_CG_NUM,
};
enum {
MT8195_AFE_IRQ_1,
MT8195_AFE_IRQ_2,
MT8195_AFE_IRQ_3,
MT8195_AFE_IRQ_8,
MT8195_AFE_IRQ_9,
MT8195_AFE_IRQ_10,
MT8195_AFE_IRQ_13,
MT8195_AFE_IRQ_14,
MT8195_AFE_IRQ_15,
MT8195_AFE_IRQ_16,
MT8195_AFE_IRQ_17,
MT8195_AFE_IRQ_18,
MT8195_AFE_IRQ_19,
MT8195_AFE_IRQ_20,
MT8195_AFE_IRQ_21,
MT8195_AFE_IRQ_22,
MT8195_AFE_IRQ_23,
MT8195_AFE_IRQ_24,
MT8195_AFE_IRQ_25,
MT8195_AFE_IRQ_26,
MT8195_AFE_IRQ_27,
MT8195_AFE_IRQ_28,
MT8195_AFE_IRQ_NUM,
};
enum {
MT8195_ETDM_OUT1_1X_EN = 9,
MT8195_ETDM_OUT2_1X_EN = 10,
MT8195_ETDM_OUT3_1X_EN = 11,
MT8195_ETDM_IN1_1X_EN = 12,
MT8195_ETDM_IN2_1X_EN = 13,
MT8195_ETDM_IN1_NX_EN = 25,
MT8195_ETDM_IN2_NX_EN = 26,
};
enum {
MT8195_MTKAIF_MISO_0,
MT8195_MTKAIF_MISO_1,
MT8195_MTKAIF_MISO_2,
MT8195_MTKAIF_MISO_NUM,
};
struct mtk_dai_memif_irq_priv {
unsigned int asys_timing_sel;
};
struct mtkaif_param {
bool mtkaif_calibration_ok;
int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM];
int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM];
int mtkaif_dmic_on;
int mtkaif_adda6_only;
};
struct clk;
struct mt8195_afe_private {
struct clk **clk;
struct clk_lookup **lookup;
struct regmap *topckgen;
int pm_runtime_bypass_reg_ctl;
#ifdef CONFIG_DEBUG_FS
struct dentry **debugfs_dentry;
#endif
int afe_on_ref_cnt;
int top_cg_ref_cnt[MT8195_TOP_CG_NUM];
spinlock_t afe_ctrl_lock; /* Lock for afe control */
struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM];
struct mtkaif_param mtkaif_params;
/* dai */
void *dai_priv[MT8195_DAI_NUM];
};
int mt8195_afe_fs_timing(unsigned int rate);
/* dai register */
int mt8195_dai_adda_register(struct mtk_base_afe *afe);
int mt8195_dai_etdm_register(struct mtk_base_afe *afe);
int mt8195_dai_pcm_register(struct mtk_base_afe *afe);
#define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
{ \
.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
.info = snd_soc_info_enum_double, \
.get = xhandler_get, .put = xhandler_put, \
.device = id, \
.private_value = (unsigned long)&xenum, \
}
#endif

3281
sound/soc/mediatek/mt8195/mt8195-afe-pcm.c Normal file
View File

File diff suppressed because it is too large Load Diff

214
sound/soc/mediatek/mt8195/mt8195-audsys-clk.c Normal file
View File

@ -0,0 +1,214 @@
// SPDX-License-Identifier: GPL-2.0
/*
* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock control
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Trevor Wu <trevor.wu@mediatek.com>
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include "mt8195-afe-common.h"
#include "mt8195-audsys-clk.h"
#include "mt8195-audsys-clkid.h"
#include "mt8195-reg.h"
struct afe_gate {
int id;
const char *name;
const char *parent_name;
int reg;
u8 bit;
const struct clk_ops *ops;
unsigned long flags;
u8 cg_flags;
};
#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.reg = _reg, \
.bit = _bit, \
.flags = _flags, \
.cg_flags = _cgflags, \
}
#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
#define GATE_AUD0(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
#define GATE_AUD1(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
#define GATE_AUD3(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
#define GATE_AUD4(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
#define GATE_AUD5(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
#define GATE_AUD6(_id, _name, _parent, _bit) \
GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
/* AUD0 */
GATE_AUD0(CLK_AUD_AFE, "aud_afe", "a1sys_hp_sel", 2),
GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "a1sys_hp_sel", 4),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "apll4_sel", 10),
GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "apll4_sel", 11),
GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "a1sys_hp_sel", 18),
GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "apll1_sel", 19),
GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "apll2_sel", 20),
GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "aud_iec_sel", 21),
GATE_AUD0(CLK_AUD_APLL, "aud_apll", "apll1_sel", 23),
GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "apll2_sel", 24),
GATE_AUD0(CLK_AUD_DAC, "aud_dac", "a1sys_hp_sel", 25),
GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "a1sys_hp_sel", 26),
GATE_AUD0(CLK_AUD_TML, "aud_tml", "a1sys_hp_sel", 27),
GATE_AUD0(CLK_AUD_ADC, "aud_adc", "a1sys_hp_sel", 28),
GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel", 31),
/* AUD1 */
GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "a1sys_hp_sel", 2),
GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "a1sys_hp_sel", 10),
GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "a1sys_hp_sel", 11),
GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "a1sys_hp_sel", 12),
GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "a1sys_hp_sel", 13),
GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "a1sys_hp_sel", 14),
GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "audio_h_sel", 16),
GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel", 17),
GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "a1sys_hp_sel", 18),
GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "audio_h_sel", 19),
/* AUD3 */
GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "apll5_sel", 5),
GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "apll3_sel", 7),
/* AUD4 */
GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "a1sys_hp_sel", 0),
GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "a1sys_hp_sel", 1),
GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "a1sys_hp_sel", 6),
GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "a1sys_hp_sel", 7),
GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "a1sys_hp_sel", 8),
GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "a1sys_hp_sel", 16),
GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "a1sys_hp_sel", 17),
GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "intdir_sel", 20),
GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "a1sys_hp_sel", 21),
GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "a2sys_sel", 22),
GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "a1sys_hp_sel", 24),
GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "a3sys_sel", 30),
GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "a4sys_sel", 31),
/* AUD5 */
GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "a1sys_hp_sel", 0),
GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "a1sys_hp_sel", 1),
GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "a1sys_hp_sel", 2),
GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "a1sys_hp_sel", 3),
GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "a1sys_hp_sel", 4),
GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "a1sys_hp_sel", 5),
GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "a1sys_hp_sel", 7),
GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "a1sys_hp_sel", 8),
GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "a1sys_hp_sel", 9),
GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "a1sys_hp_sel", 18),
GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "a1sys_hp_sel", 19),
GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "a1sys_hp_sel", 22),
GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "a1sys_hp_sel", 23),
GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "a1sys_hp_sel", 24),
GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "a1sys_hp_sel", 26),
GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "a1sys_hp_sel", 27),
/* AUD6 */
GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "asm_h_sel", 0),
GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "asm_h_sel", 1),
GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "asm_h_sel", 2),
GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "asm_h_sel", 3),
GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "asm_h_sel", 4),
GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "asm_h_sel", 5),
GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "asm_h_sel", 6),
GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "asm_h_sel", 7),
GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "asm_h_sel", 8),
GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "asm_h_sel", 9),
GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "asm_h_sel", 10),
GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "asm_h_sel", 11),
GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "asm_h_sel", 12),
GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "asm_h_sel", 13),
GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "asm_h_sel", 14),
GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "asm_h_sel", 15),
GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "asm_h_sel", 16),
GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "asm_h_sel", 17),
GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "asm_h_sel", 18),
GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "asm_h_sel", 19),
};
int mt8195_audsys_clk_register(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
sizeof(*afe_priv->lookup),
GFP_KERNEL);
if (!afe_priv->lookup)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
const struct afe_gate *gate = &aud_clks[i];
clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
gate->flags, afe->base_addr + gate->reg,
gate->bit, gate->cg_flags, NULL);
if (IS_ERR(clk)) {
dev_err(afe->dev, "Failed to register clk %s: %ld\n",
gate->name, PTR_ERR(clk));
continue;
}
/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
cl = kzalloc(sizeof(*cl), GFP_KERNEL);
if (!cl)
return -ENOMEM;
cl->clk = clk;
cl->con_id = gate->name;
cl->dev_id = dev_name(afe->dev);
clkdev_add(cl);
afe_priv->lookup[i] = cl;
}
return 0;
}
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk;
struct clk_lookup *cl;
int i;
if (!afe_priv)
return;
for (i = 0; i < CLK_AUD_NR_CLK; i++) {
cl = afe_priv->lookup[i];
if (!cl)
continue;
clk = cl->clk;
clk_unregister_gate(clk);
clkdev_drop(cl);
}
}

15
sound/soc/mediatek/mt8195/mt8195-audsys-clk.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Trevor Wu <trevor.wu@mediatek.com>
*/
#ifndef _MT8195_AUDSYS_CLK_H_
#define _MT8195_AUDSYS_CLK_H_
int mt8195_audsys_clk_register(struct mtk_base_afe *afe);
void mt8195_audsys_clk_unregister(struct mtk_base_afe *afe);
#endif

93
sound/soc/mediatek/mt8195/mt8195-audsys-clkid.h Normal file
View File

@ -0,0 +1,93 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Trevor Wu <trevor.wu@mediatek.com>
*/
#ifndef _MT8195_AUDSYS_CLKID_H_
#define _MT8195_AUDSYS_CLKID_H_
enum{
CLK_AUD_AFE,
CLK_AUD_LRCK_CNT,
CLK_AUD_SPDIFIN_TUNER_APLL,
CLK_AUD_SPDIFIN_TUNER_DBG,
CLK_AUD_UL_TML,
CLK_AUD_APLL1_TUNER,
CLK_AUD_APLL2_TUNER,
CLK_AUD_TOP0_SPDF,
CLK_AUD_APLL,
CLK_AUD_APLL2,
CLK_AUD_DAC,
CLK_AUD_DAC_PREDIS,
CLK_AUD_TML,
CLK_AUD_ADC,
CLK_AUD_DAC_HIRES,
CLK_AUD_A1SYS_HP,
CLK_AUD_AFE_DMIC1,
CLK_AUD_AFE_DMIC2,
CLK_AUD_AFE_DMIC3,
CLK_AUD_AFE_DMIC4,
CLK_AUD_AFE_26M_DMIC_TM,
CLK_AUD_UL_TML_HIRES,
CLK_AUD_ADC_HIRES,
CLK_AUD_ADDA6_ADC,
CLK_AUD_ADDA6_ADC_HIRES,
CLK_AUD_LINEIN_TUNER,
CLK_AUD_EARC_TUNER,
CLK_AUD_I2SIN,
CLK_AUD_TDM_IN,
CLK_AUD_I2S_OUT,
CLK_AUD_TDM_OUT,
CLK_AUD_HDMI_OUT,
CLK_AUD_ASRC11,
CLK_AUD_ASRC12,
CLK_AUD_MULTI_IN,
CLK_AUD_INTDIR,
CLK_AUD_A1SYS,
CLK_AUD_A2SYS,
CLK_AUD_PCMIF,
CLK_AUD_A3SYS,
CLK_AUD_A4SYS,
CLK_AUD_MEMIF_UL1,
CLK_AUD_MEMIF_UL2,
CLK_AUD_MEMIF_UL3,
CLK_AUD_MEMIF_UL4,
CLK_AUD_MEMIF_UL5,
CLK_AUD_MEMIF_UL6,
CLK_AUD_MEMIF_UL8,
CLK_AUD_MEMIF_UL9,
CLK_AUD_MEMIF_UL10,
CLK_AUD_MEMIF_DL2,
CLK_AUD_MEMIF_DL3,
CLK_AUD_MEMIF_DL6,
CLK_AUD_MEMIF_DL7,
CLK_AUD_MEMIF_DL8,
CLK_AUD_MEMIF_DL10,
CLK_AUD_MEMIF_DL11,
CLK_AUD_GASRC0,
CLK_AUD_GASRC1,
CLK_AUD_GASRC2,
CLK_AUD_GASRC3,
CLK_AUD_GASRC4,
CLK_AUD_GASRC5,
CLK_AUD_GASRC6,
CLK_AUD_GASRC7,
CLK_AUD_GASRC8,
CLK_AUD_GASRC9,
CLK_AUD_GASRC10,
CLK_AUD_GASRC11,
CLK_AUD_GASRC12,
CLK_AUD_GASRC13,
CLK_AUD_GASRC14,
CLK_AUD_GASRC15,
CLK_AUD_GASRC16,
CLK_AUD_GASRC17,
CLK_AUD_GASRC18,
CLK_AUD_GASRC19,
CLK_AUD_NR_CLK,
};
#endif

830
sound/soc/mediatek/mt8195/mt8195-dai-adda.c Normal file
View File

@ -0,0 +1,830 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI ADDA Control
*
* Copyright (c) 2021 MediaTek Inc.
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
* Trevor Wu <trevor.wu@mediatek.com>
*/
#include <linux/delay.h>
#include <linux/regmap.h>
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#include "mt8195-reg.h"
#define ADDA_DL_GAIN_LOOPBACK 0x1800
#define ADDA_HIRES_THRES 48000
enum {
SUPPLY_SEQ_CLOCK_SEL,
SUPPLY_SEQ_CLOCK_ON,
SUPPLY_SEQ_ADDA_DL_ON,
SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SUPPLY_SEQ_ADDA_UL_ON,
SUPPLY_SEQ_ADDA_AFE_ON,
};
enum {
MTK_AFE_ADDA_DL_RATE_8K = 0,
MTK_AFE_ADDA_DL_RATE_11K = 1,
MTK_AFE_ADDA_DL_RATE_12K = 2,
MTK_AFE_ADDA_DL_RATE_16K = 3,
MTK_AFE_ADDA_DL_RATE_22K = 4,
MTK_AFE_ADDA_DL_RATE_24K = 5,
MTK_AFE_ADDA_DL_RATE_32K = 6,
MTK_AFE_ADDA_DL_RATE_44K = 7,
MTK_AFE_ADDA_DL_RATE_48K = 8,
MTK_AFE_ADDA_DL_RATE_96K = 9,
MTK_AFE_ADDA_DL_RATE_192K = 10,
};
enum {
MTK_AFE_ADDA_UL_RATE_8K = 0,
MTK_AFE_ADDA_UL_RATE_16K = 1,
MTK_AFE_ADDA_UL_RATE_32K = 2,
MTK_AFE_ADDA_UL_RATE_48K = 3,
MTK_AFE_ADDA_UL_RATE_96K = 4,
MTK_AFE_ADDA_UL_RATE_192K = 5,
};
enum {
DELAY_DATA_MISO1 = 0,
DELAY_DATA_MISO0 = 1,
DELAY_DATA_MISO2 = 1,
};
enum {
MTK_AFE_ADDA,
MTK_AFE_ADDA6,
};
struct mtk_dai_adda_priv {
bool hires_required;
};
static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_DL_RATE_8K;
case 11025:
return MTK_AFE_ADDA_DL_RATE_11K;
case 12000:
return MTK_AFE_ADDA_DL_RATE_12K;
case 16000:
return MTK_AFE_ADDA_DL_RATE_16K;
case 22050:
return MTK_AFE_ADDA_DL_RATE_22K;
case 24000:
return MTK_AFE_ADDA_DL_RATE_24K;
case 32000:
return MTK_AFE_ADDA_DL_RATE_32K;
case 44100:
return MTK_AFE_ADDA_DL_RATE_44K;
case 48000:
return MTK_AFE_ADDA_DL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_DL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_DL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_DL_RATE_48K;
}
}
static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe,
unsigned int rate)
{
switch (rate) {
case 8000:
return MTK_AFE_ADDA_UL_RATE_8K;
case 16000:
return MTK_AFE_ADDA_UL_RATE_16K;
case 32000:
return MTK_AFE_ADDA_UL_RATE_32K;
case 48000:
return MTK_AFE_ADDA_UL_RATE_48K;
case 96000:
return MTK_AFE_ADDA_UL_RATE_96K;
case 192000:
return MTK_AFE_ADDA_UL_RATE_192K;
default:
dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
__func__, rate);
return MTK_AFE_ADDA_UL_RATE_48K;
}
}
static int mt8195_adda_mtkaif_init(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int delay_data;
int delay_cycle;
unsigned int mask = 0;
unsigned int val = 0;
/* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */
mask = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
val = (MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2);
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, mask, val);
regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, mask, val);
mask = RG_RX_PROTOCOL2;
val = RG_RX_PROTOCOL2;
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, mask, val);
if (!param->mtkaif_calibration_ok) {
dev_info(afe->dev, "%s(), calibration fail\n", __func__);
return 0;
}
/* set delay for ch1, ch2 */
if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] >=
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
} else {
delay_data = DELAY_DATA_MISO0;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_0];
}
val = 0;
mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
MTKAIF_RXIF_DELAY_CYCLE_MASK;
val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val);
/* set delay between ch3 and ch2 */
if (param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] >=
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1]) {
delay_data = DELAY_DATA_MISO1;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1];
} else {
delay_data = DELAY_DATA_MISO2;
delay_cycle =
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_1] -
param->mtkaif_phase_cycle[MT8195_MTKAIF_MISO_2];
}
val = 0;
mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK);
val |= MTKAIF_RXIF_DELAY_CYCLE(delay_cycle) &
MTKAIF_RXIF_DELAY_CYCLE_MASK;
val |= delay_data << MTKAIF_RXIF_DELAY_DATA_SHIFT;
regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_RX_CFG2, mask, val);
return 0;
}
static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mt8195_adda_mtkaif_init(afe);
break;
default:
break;
}
return 0;
}
static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, int adda, bool dmic)
{
unsigned int reg = 0;
unsigned int mask = 0;
unsigned int val = 0;
switch (adda) {
case MTK_AFE_ADDA:
reg = AFE_ADDA_UL_SRC_CON0;
break;
case MTK_AFE_ADDA6:
reg = AFE_ADDA6_UL_SRC_CON0;
break;
default:
dev_info(afe->dev, "%s(), wrong parameter\n", __func__);
return;
}
mask = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL |
UL_MODE_3P25M_CH2_CTL);
/* turn on dmic, ch1, ch2 */
if (dmic)
val = mask;
regmap_update_bits(afe->regmap, reg, mask, val);
}
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_adda_ul_mictype(afe, MTK_AFE_ADDA, param->mtkaif_dmic_on);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static int mtk_adda6_ul_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
unsigned int val;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
mtk_adda_ul_mictype(afe, MTK_AFE_ADDA6, param->mtkaif_dmic_on);
val = (param->mtkaif_adda6_only ?
ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE : 0);
regmap_update_bits(afe->regmap,
AFE_ADDA_MTKAIF_SYNCWORD_CFG,
ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE,
val);
break;
case SND_SOC_DAPM_POST_PMD:
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
usleep_range(125, 135);
break;
default:
break;
}
return 0;
}
static int mtk_audio_hires_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct clk *clk = afe_priv->clk[MT8195_CLK_TOP_AUDIO_H_SEL];
struct clk *clk_parent;
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
__func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
clk_parent = afe_priv->clk[MT8195_CLK_TOP_APLL1];
break;
case SND_SOC_DAPM_POST_PMD:
clk_parent = afe_priv->clk[MT8195_CLK_XTAL_26M];
break;
default:
return 0;
}
mt8195_afe_set_clk_parent(afe, clk, clk_parent);
return 0;
}
static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,
const char *name)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
int dai_id;
if (strstr(name, "aud_adc_hires"))
dai_id = MT8195_AFE_IO_UL_SRC1;
else if (strstr(name, "aud_adda6_adc_hires"))
dai_id = MT8195_AFE_IO_UL_SRC2;
else if (strstr(name, "aud_dac_hires"))
dai_id = MT8195_AFE_IO_DL_SRC;
else
return NULL;
return afe_priv->dai_priv[dai_id];
}
static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_dapm_widget *w = source;
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mtk_dai_adda_priv *adda_priv;
adda_priv = get_adda_priv_by_name(afe, w->name);
if (!adda_priv) {
dev_info(afe->dev, "adda_priv == NULL");
return 0;
}
return (adda_priv->hires_required) ? 1 : 0;
}
static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0),
};
static const char * const adda_dlgain_mux_map[] = {
"Bypass", "Connect",
};
static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum,
SND_SOC_NOPM, 0,
adda_dlgain_mux_map);
static const struct snd_kcontrol_new adda_dlgain_mux_control =
SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum);
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I170", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I171", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o176_mix,
ARRAY_SIZE(mtk_dai_adda_o176_mix)),
SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0,
mtk_dai_adda_o177_mix,
ARRAY_SIZE(mtk_dai_adda_o177_mix)),
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
AFE_ADDA_UL_DL_CON0,
ADDA_AFE_ON_SHIFT, 0,
NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
AFE_ADDA_DL_SRC2_CON0,
DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0,
mtk_adda_dl_event,
SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SHIFT, 0,
mtk_adda_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA6 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
AFE_ADDA6_UL_SRC_CON0,
UL_SRC_ON_TMP_CTL_SHIFT, 0,
mtk_adda6_ul_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("AUDIO_HIRES", SUPPLY_SEQ_CLOCK_SEL,
SND_SOC_NOPM,
0, 0,
mtk_audio_hires_event,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
SND_SOC_NOPM,
0, 0,
mtk_adda_mtkaif_cfg_event,
SND_SOC_DAPM_PRE_PMU),
SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0,
&adda_dlgain_mux_control),
SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0,
DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_INPUT("ADDA_INPUT"),
SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"),
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_hires"),
};
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
{"ADDA Capture", NULL, "ADDA Enable"},
{"ADDA Capture", NULL, "ADDA Capture Enable"},
{"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA Capture", NULL, "aud_adc"},
{"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect},
{"aud_adc_hires", NULL, "AUDIO_HIRES"},
{"ADDA6 Capture", NULL, "ADDA Enable"},
{"ADDA6 Capture", NULL, "ADDA6 Capture Enable"},
{"ADDA6 Capture", NULL, "ADDA_MTKAIF_CFG"},
{"ADDA6 Capture", NULL, "aud_adda6_adc"},
{"ADDA6 Capture", NULL, "aud_adda6_adc_hires",
mtk_afe_adda_hires_connect},
{"aud_adda6_adc_hires", NULL, "AUDIO_HIRES"},
{"I168", NULL, "ADDA Capture"},
{"I169", NULL, "ADDA Capture"},
{"I170", NULL, "ADDA6 Capture"},
{"I171", NULL, "ADDA6 Capture"},
{"ADDA Playback", NULL, "ADDA Enable"},
{"ADDA Playback", NULL, "ADDA Playback Enable"},
{"ADDA Playback", NULL, "aud_dac"},
{"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect},
{"aud_dac_hires", NULL, "AUDIO_HIRES"},
{"DL_GAIN", NULL, "O176"},
{"DL_GAIN", NULL, "O177"},
{"DL_GAIN_MUX", "Bypass", "O176"},
{"DL_GAIN_MUX", "Bypass", "O177"},
{"DL_GAIN_MUX", "Connect", "DL_GAIN"},
{"ADDA Playback", NULL, "DL_GAIN_MUX"},
{"O176", "I000 Switch", "I000"},
{"O177", "I001 Switch", "I001"},
{"O176", "I002 Switch", "I002"},
{"O177", "I003 Switch", "I003"},
{"O176", "I020 Switch", "I020"},
{"O177", "I021 Switch", "I021"},
{"O176", "I022 Switch", "I022"},
{"O177", "I023 Switch", "I023"},
{"O176", "I070 Switch", "I070"},
{"O177", "I071 Switch", "I071"},
{"ADDA Capture", NULL, "ADDA_INPUT"},
{"ADDA6 Capture", NULL, "ADDA_INPUT"},
{"ADDA_OUTPUT", NULL, "ADDA Playback"},
};
static int mt8195_adda_dl_gain_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
unsigned int value = (unsigned int)(ucontrol->value.integer.value[0]);
regmap_update_bits(afe->regmap, reg, mask, DL_2_GAIN_CTL_PRE(value));
return 0;
}
static int mt8195_adda_dl_gain_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
unsigned int reg = AFE_ADDA_DL_SRC2_CON1;
unsigned int mask = DL_2_GAIN_CTL_PRE_MASK;
unsigned int value = 0;
regmap_read(afe->regmap, reg, &value);
ucontrol->value.integer.value[0] = ((value & mask) >>
DL_2_GAIN_CTL_PRE_SHIFT);
return 0;
}
static int mt8195_adda6_only_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
ucontrol->value.integer.value[0] = param->mtkaif_adda6_only;
return 0;
}
static int mt8195_adda6_only_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int mtkaif_adda6_only;
mtkaif_adda6_only = ucontrol->value.integer.value[0];
dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
__func__, kcontrol->id.name, mtkaif_adda6_only);
param->mtkaif_adda6_only = mtkaif_adda6_only;
return 0;
}
static int mt8195_adda_dmic_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
ucontrol->value.integer.value[0] = param->mtkaif_dmic_on;
return 0;
}
static int mt8195_adda_dmic_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtkaif_param *param = &afe_priv->mtkaif_params;
int dmic_on;
dmic_on = ucontrol->value.integer.value[0];
dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
__func__, kcontrol->id.name, dmic_on);
param->mtkaif_dmic_on = dmic_on;
return 0;
}
static const struct snd_kcontrol_new mtk_dai_adda_controls[] = {
SOC_SINGLE_EXT("ADDA_DL_Gain", SND_SOC_NOPM, 0, 65535, 0,
mt8195_adda_dl_gain_get, mt8195_adda_dl_gain_put),
SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC", 0,
mt8195_adda_dmic_get, mt8195_adda_dmic_set),
SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY", 0,
mt8195_adda6_only_get,
mt8195_adda6_only_set),
};
static int mtk_dai_da_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val = 0;
unsigned int mask = 0;
/* set sampling rate */
mask |= DL_2_INPUT_MODE_CTL_MASK;
val |= DL_2_INPUT_MODE_CTL(afe_adda_dl_rate_transform(afe, rate));
/* turn off saturation */
mask |= DL_2_CH1_SATURATION_EN_CTL;
mask |= DL_2_CH2_SATURATION_EN_CTL;
/* turn off mute function */
mask |= DL_2_MUTE_CH1_OFF_CTL_PRE;
mask |= DL_2_MUTE_CH2_OFF_CTL_PRE;
val |= DL_2_MUTE_CH1_OFF_CTL_PRE;
val |= DL_2_MUTE_CH2_OFF_CTL_PRE;
/* set voice input data if input sample rate is 8k or 16k */
mask |= DL_2_VOICE_MODE_CTL_PRE;
if (rate == 8000 || rate == 16000)
val |= DL_2_VOICE_MODE_CTL_PRE;
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val);
mask = 0;
val = 0;
/* new 2nd sdm */
mask |= DL_USE_NEW_2ND_SDM;
val |= DL_USE_NEW_2ND_SDM;
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, mask, val);
return 0;
}
static int mtk_dai_ad_configure(struct mtk_base_afe *afe,
unsigned int rate, int id)
{
unsigned int val = 0;
unsigned int mask = 0;
mask |= UL_VOICE_MODE_CTL_MASK;
val |= UL_VOICE_MODE_CTL(afe_adda_ul_rate_transform(afe, rate));
switch (id) {
case MT8195_AFE_IO_UL_SRC1:
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
mask, val);
break;
case MT8195_AFE_IO_UL_SRC2:
regmap_update_bits(afe->regmap, AFE_ADDA6_UL_SRC_CON0,
mask, val);
break;
default:
break;
}
return 0;
}
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id];
unsigned int rate = params_rate(params);
int id = dai->id;
int ret = 0;
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
__func__, id, substream->stream, rate);
if (rate > ADDA_HIRES_THRES)
adda_priv->hires_required = 1;
else
adda_priv->hires_required = 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
ret = mtk_dai_da_configure(afe, rate, id);
else
ret = mtk_dai_ad_configure(afe, rate, id);
return ret;
}
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
.hw_params = mtk_dai_adda_hw_params,
};
/* dai driver */
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 |\
SNDRV_PCM_RATE_48000 |\
SNDRV_PCM_RATE_96000 |\
SNDRV_PCM_RATE_192000)
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
{
.name = "DL_SRC",
.id = MT8195_AFE_IO_DL_SRC,
.playback = {
.stream_name = "ADDA Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_PLAYBACK_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "UL_SRC1",
.id = MT8195_AFE_IO_UL_SRC1,
.capture = {
.stream_name = "ADDA Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
{
.name = "UL_SRC2",
.id = MT8195_AFE_IO_UL_SRC2,
.capture = {
.stream_name = "ADDA6 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_ADDA_CAPTURE_RATES,
.formats = MTK_ADDA_FORMATS,
},
.ops = &mtk_dai_adda_ops,
},
};
static int init_adda_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_adda_priv *adda_priv;
int adda_dai_list[] = { MT8195_AFE_IO_DL_SRC,
MT8195_AFE_IO_UL_SRC1,
MT8195_AFE_IO_UL_SRC2};
int i;
for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) {
adda_priv = devm_kzalloc(afe->dev,
sizeof(struct mtk_dai_adda_priv),
GFP_KERNEL);
if (!adda_priv)
return -ENOMEM;
afe_priv->dai_priv[adda_dai_list[i]] = adda_priv;
}
return 0;
}
int mt8195_dai_adda_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_adda_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
dai->dapm_widgets = mtk_dai_adda_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
dai->dapm_routes = mtk_dai_adda_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
dai->controls = mtk_dai_adda_controls;
dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls);
return init_adda_priv_data(afe);
}

2639
sound/soc/mediatek/mt8195/mt8195-dai-etdm.c Normal file
View File

File diff suppressed because it is too large Load Diff

389
sound/soc/mediatek/mt8195/mt8195-dai-pcm.c Normal file
View File

@ -0,0 +1,389 @@
// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek ALSA SoC Audio DAI PCM I/F Control
*
* Copyright (c) 2020 MediaTek Inc.
* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
* Trevor Wu <trevor.wu@mediatek.com>
*/
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include "mt8195-afe-clk.h"
#include "mt8195-afe-common.h"
#include "mt8195-reg.h"
enum {
MTK_DAI_PCM_FMT_I2S,
MTK_DAI_PCM_FMT_EIAJ,
MTK_DAI_PCM_FMT_MODEA,
MTK_DAI_PCM_FMT_MODEB,
};
enum {
MTK_DAI_PCM_CLK_A1SYS,
MTK_DAI_PCM_CLK_A2SYS,
MTK_DAI_PCM_CLK_26M_48K,
MTK_DAI_PCM_CLK_26M_441K,
};
struct mtk_dai_pcm_rate {
unsigned int rate;
unsigned int reg_value;
};
struct mtk_dai_pcmif_priv {
unsigned int slave_mode;
unsigned int lrck_inv;
unsigned int bck_inv;
unsigned int format;
};
static const struct mtk_dai_pcm_rate mtk_dai_pcm_rates[] = {
{ .rate = 8000, .reg_value = 0, },
{ .rate = 16000, .reg_value = 1, },
{ .rate = 32000, .reg_value = 2, },
{ .rate = 48000, .reg_value = 3, },
{ .rate = 11025, .reg_value = 1, },
{ .rate = 22050, .reg_value = 2, },
{ .rate = 44100, .reg_value = 3, },
};
static int mtk_dai_pcm_mode(unsigned int rate)
{
int i;
for (i = 0; i < ARRAY_SIZE(mtk_dai_pcm_rates); i++)
if (mtk_dai_pcm_rates[i].rate == rate)
return mtk_dai_pcm_rates[i].reg_value;
return -EINVAL;
}
static const struct snd_kcontrol_new mtk_dai_pcm_o000_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN0, 0, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN0_2, 6, 1, 0),
};
static const struct snd_kcontrol_new mtk_dai_pcm_o001_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN1, 1, 1, 0),
SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN1_2, 7, 1, 0),
};
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
SND_SOC_DAPM_MIXER("I002", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("I003", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_MIXER("O000", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o000_mix,
ARRAY_SIZE(mtk_dai_pcm_o000_mix)),
SND_SOC_DAPM_MIXER("O001", SND_SOC_NOPM, 0, 0,
mtk_dai_pcm_o001_mix,
ARRAY_SIZE(mtk_dai_pcm_o001_mix)),
SND_SOC_DAPM_INPUT("PCM1_INPUT"),
SND_SOC_DAPM_OUTPUT("PCM1_OUTPUT"),
};
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
{"I002", NULL, "PCM1 Capture"},
{"I003", NULL, "PCM1 Capture"},
{"O000", "I000 Switch", "I000"},
{"O001", "I001 Switch", "I001"},
{"O000", "I070 Switch", "I070"},
{"O001", "I071 Switch", "I071"},
{"PCM1 Playback", NULL, "O000"},
{"PCM1 Playback", NULL, "O001"},
{"PCM1_OUTPUT", NULL, "PCM1 Playback"},
{"PCM1 Capture", NULL, "PCM1_INPUT"},
};
static void mtk_dai_pcm_enable(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
PCM_INTF_CON1_PCM_EN, PCM_INTF_CON1_PCM_EN);
}
static void mtk_dai_pcm_disable(struct mtk_base_afe *afe)
{
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
PCM_INTF_CON1_PCM_EN, 0x0);
}
static int mtk_dai_pcm_configure(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_pcm_runtime * const runtime = substream->runtime;
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv = afe_priv->dai_priv[dai->id];
unsigned int slave_mode = pcmif_priv->slave_mode;
unsigned int lrck_inv = pcmif_priv->lrck_inv;
unsigned int bck_inv = pcmif_priv->bck_inv;
unsigned int fmt = pcmif_priv->format;
unsigned int bit_width = dai->sample_bits;
unsigned int val = 0;
unsigned int mask = 0;
int fs = 0;
int mode = 0;
/* sync freq mode */
fs = mt8195_afe_fs_timing(runtime->rate);
if (fs < 0)
return -EINVAL;
val |= PCM_INTF_CON2_SYNC_FREQ_MODE(fs);
mask |= PCM_INTF_CON2_SYNC_FREQ_MODE_MASK;
/* clk domain sel */
if (runtime->rate % 8000)
val |= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_441K);
else
val |= PCM_INTF_CON2_CLK_DOMAIN_SEL(MTK_DAI_PCM_CLK_26M_48K);
mask |= PCM_INTF_CON2_CLK_DOMAIN_SEL_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON2, mask, val);
val = 0;
mask = 0;
/* pcm mode */
mode = mtk_dai_pcm_mode(runtime->rate);
if (mode < 0)
return -EINVAL;
val |= PCM_INTF_CON1_PCM_MODE(mode);
mask |= PCM_INTF_CON1_PCM_MODE_MASK;
/* pcm format */
val |= PCM_INTF_CON1_PCM_FMT(fmt);
mask |= PCM_INTF_CON1_PCM_FMT_MASK;
/* pcm sync length */
if (fmt == MTK_DAI_PCM_FMT_MODEA ||
fmt == MTK_DAI_PCM_FMT_MODEB)
val |= PCM_INTF_CON1_SYNC_LENGTH(1);
else
val |= PCM_INTF_CON1_SYNC_LENGTH(bit_width);
mask |= PCM_INTF_CON1_SYNC_LENGTH_MASK;
/* pcm bits, word length */
if (bit_width > 16) {
val |= PCM_INTF_CON1_PCM_24BIT;
val |= PCM_INTF_CON1_PCM_WLEN_64BCK;
} else {
val |= PCM_INTF_CON1_PCM_16BIT;
val |= PCM_INTF_CON1_PCM_WLEN_32BCK;
}
mask |= PCM_INTF_CON1_PCM_BIT_MASK;
mask |= PCM_INTF_CON1_PCM_WLEN_MASK;
/* master/slave */
if (!slave_mode) {
val |= PCM_INTF_CON1_PCM_MASTER;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_OUT_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_OUT_INV;
mask |= PCM_INTF_CON1_CLK_OUT_INV_MASK;
} else {
val |= PCM_INTF_CON1_PCM_SLAVE;
if (lrck_inv)
val |= PCM_INTF_CON1_SYNC_IN_INV;
if (bck_inv)
val |= PCM_INTF_CON1_BCLK_IN_INV;
mask |= PCM_INTF_CON1_CLK_IN_INV_MASK;
/* TODO: add asrc setting for slave mode */
}
mask |= PCM_INTF_CON1_PCM_M_S_MASK;
regmap_update_bits(afe->regmap, PCM_INTF_CON1, mask, val);
return 0;
}
/* dai ops */
static int mtk_dai_pcm_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
if (dai->component->active)
return 0;
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC11]);
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC12]);
mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_PCMIF]);
return 0;
}
static void mtk_dai_pcm_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
if (dai->component->active)
return;
mtk_dai_pcm_disable(afe);
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_PCMIF]);
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC12]);
mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_ASRC11]);
}
static int mtk_dai_pcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
int ret = 0;
if (snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK) &&
snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE))
return 0;
ret = mtk_dai_pcm_configure(substream, dai);
if (ret)
return ret;
mtk_dai_pcm_enable(afe);
return 0;
}
static int mtk_dai_pcm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv = afe_priv->dai_priv[dai->id];
dev_dbg(dai->dev, "%s fmt 0x%x\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
pcmif_priv->format = MTK_DAI_PCM_FMT_I2S;
break;
case SND_SOC_DAIFMT_DSP_A:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEA;
break;
case SND_SOC_DAIFMT_DSP_B:
pcmif_priv->format = MTK_DAI_PCM_FMT_MODEB;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_NB_IF:
pcmif_priv->bck_inv = 0;
pcmif_priv->lrck_inv = 1;
break;
case SND_SOC_DAIFMT_IB_NF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 0;
break;
case SND_SOC_DAIFMT_IB_IF:
pcmif_priv->bck_inv = 1;
pcmif_priv->lrck_inv = 1;
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
pcmif_priv->slave_mode = 1;
break;
case SND_SOC_DAIFMT_CBS_CFS:
pcmif_priv->slave_mode = 0;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
.startup = mtk_dai_pcm_startup,
.shutdown = mtk_dai_pcm_shutdown,
.prepare = mtk_dai_pcm_prepare,
.set_fmt = mtk_dai_pcm_set_fmt,
};
/* dai driver */
#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000)
#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
{
.name = "PCM1",
.id = MT8195_AFE_IO_PCM,
.playback = {
.stream_name = "PCM1 Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.capture = {
.stream_name = "PCM1 Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MTK_PCM_RATES,
.formats = MTK_PCM_FORMATS,
},
.ops = &mtk_dai_pcm_ops,
.symmetric_rate = 1,
.symmetric_sample_bits = 1,
},
};
static int init_pcmif_priv_data(struct mtk_base_afe *afe)
{
struct mt8195_afe_private *afe_priv = afe->platform_priv;
struct mtk_dai_pcmif_priv *pcmif_priv;
pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_pcmif_priv),
GFP_KERNEL);
if (!pcmif_priv)
return -ENOMEM;
afe_priv->dai_priv[MT8195_AFE_IO_PCM] = pcmif_priv;
return 0;
}
int mt8195_dai_pcm_register(struct mtk_base_afe *afe)
{
struct mtk_base_afe_dai *dai;
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
if (!dai)
return -ENOMEM;
list_add(&dai->list, &afe->sub_dais);
dai->dai_drivers = mtk_dai_pcm_driver;
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
dai->dapm_widgets = mtk_dai_pcm_widgets;
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
dai->dapm_routes = mtk_dai_pcm_routes;
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
return init_pcmif_priv_data(afe);
}

1087
sound/soc/mediatek/mt8195/mt8195-mt6359-rt1019-rt5682.c Normal file
View File

File diff suppressed because it is too large Load Diff

2796
sound/soc/mediatek/mt8195/mt8195-reg.h Normal file
View File

File diff suppressed because it is too large Load Diff