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net: ethernet: mtk_eth_soc: enable nft hw flowtable_offload for MT7988 SoC

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Enable hw Packet Process Engine (PPE) for MT7988 SoC.

Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lorenzo Bianconi 2023-07-27 09:07:28 +02:00 committed by Jakub Kicinski
parent 58ea461b69
commit 88efedf517
3 changed files with 36 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/ethernet/mediatek/mtk_eth_soc.c
View File

@ -5062,6 +5062,9 @@ static const struct mtk_soc_data mt7988_data = {
.required_clks = MT7988_CLKS_BITMAP, .required_clks = MT7988_CLKS_BITMAP,
.required_pctl = false, .required_pctl = false,
.version = 3, .version = 3,
.offload_version = 2,
.hash_offset = 4,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
.txrx = { .txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2), .txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2),

19
drivers/net/ethernet/mediatek/mtk_ppe.c
View File

@ -423,13 +423,22 @@ int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
u32 *ib2 = mtk_foe_entry_ib2(eth, entry); u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
if (mtk_is_netsys_v2_or_greater(eth)) { switch (eth->soc->version) {
case 3:
*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
*ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
MTK_FOE_IB2_WDMA_WINFO_V2;
l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
break;
case 2:
*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
*ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
MTK_FOE_IB2_WDMA_WINFO_V2; MTK_FOE_IB2_WDMA_WINFO_V2;
l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
FIELD_PREP(MTK_FOE_WINFO_BSS, bss); FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
} else { break;
default:
*ib2 &= ~MTK_FOE_IB2_PORT_MG; *ib2 &= ~MTK_FOE_IB2_PORT_MG;
*ib2 |= MTK_FOE_IB2_WDMA_WINFO; *ib2 |= MTK_FOE_IB2_WDMA_WINFO;
if (wdma_idx) if (wdma_idx)
@ -437,6 +446,7 @@ int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
break;
} }
return 0; return 0;
@ -964,8 +974,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
mtk_ppe_init_foe_table(ppe); mtk_ppe_init_foe_table(ppe);
ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
val = MTK_PPE_TB_CFG_ENTRY_80B | val = MTK_PPE_TB_CFG_AGE_NON_L4 |
MTK_PPE_TB_CFG_AGE_NON_L4 |
MTK_PPE_TB_CFG_AGE_UNBIND | MTK_PPE_TB_CFG_AGE_UNBIND |
MTK_PPE_TB_CFG_AGE_TCP | MTK_PPE_TB_CFG_AGE_TCP |
MTK_PPE_TB_CFG_AGE_UDP | MTK_PPE_TB_CFG_AGE_UDP |
@ -981,6 +990,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
MTK_PPE_ENTRIES_SHIFT); MTK_PPE_ENTRIES_SHIFT);
if (mtk_is_netsys_v2_or_greater(ppe->eth)) if (mtk_is_netsys_v2_or_greater(ppe->eth))
val |= MTK_PPE_TB_CFG_INFO_SEL; val |= MTK_PPE_TB_CFG_INFO_SEL;
if (!mtk_is_netsys_v3_or_greater(ppe->eth))
val |= MTK_PPE_TB_CFG_ENTRY_80B;
ppe_w32(ppe, MTK_PPE_TB_CFG, val); ppe_w32(ppe, MTK_PPE_TB_CFG, val);
ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK, ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,

19
drivers/net/ethernet/mediatek/mtk_ppe.h
View File

@ -85,6 +85,17 @@ enum {
#define MTK_FOE_WINFO_BSS GENMASK(5, 0) #define MTK_FOE_WINFO_BSS GENMASK(5, 0)
#define MTK_FOE_WINFO_WCID GENMASK(15, 6) #define MTK_FOE_WINFO_WCID GENMASK(15, 6)
#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16)
#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0)
#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0)
#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16)
#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20)
#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21)
#define MTK_FOE_WINFO_PAO_IS_SP BIT(22)
#define MTK_FOE_WINFO_PAO_HF BIT(23)
#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24)
enum { enum {
MTK_FOE_STATE_INVALID, MTK_FOE_STATE_INVALID,
MTK_FOE_STATE_UNBIND, MTK_FOE_STATE_UNBIND,
@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
u16 pppoe_id; u16 pppoe_id;
u16 src_mac_lo; u16 src_mac_lo;
/* netsys_v2 */
u16 minfo; u16 minfo;
u16 winfo; u16 winfo;
/* netsys_v3 */
u32 w3info;
u32 wpao;
}; };
/* software-only entry type */ /* software-only entry type */
@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
#define MTK_FOE_ENTRY_V1_SIZE 80 #define MTK_FOE_ENTRY_V1_SIZE 80
#define MTK_FOE_ENTRY_V2_SIZE 96 #define MTK_FOE_ENTRY_V2_SIZE 96
#define MTK_FOE_ENTRY_V3_SIZE 128
struct mtk_foe_entry { struct mtk_foe_entry {
u32 ib1; u32 ib1;
@ -228,7 +245,7 @@ struct mtk_foe_entry {
struct mtk_foe_ipv4_dslite dslite; struct mtk_foe_ipv4_dslite dslite;
struct mtk_foe_ipv6 ipv6; struct mtk_foe_ipv6 ipv6;
struct mtk_foe_ipv6_6rd ipv6_6rd; struct mtk_foe_ipv6_6rd ipv6_6rd;
u32 data[23]; u32 data[31];
}; };
}; };