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mlxsw: Add SMPE related fields to SMID2 register

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SMID register maps multicast ID (MID) into a list of local ports.
As preparation for unified bridge model, add some required fields for
future use.

The device includes two main tables to support layer 2 multicast (i.e.,
MDB and flooding). These are the PGT (Port Group Table) and the
MPE (Multicast Port Egress) table.
- PGT is {MID -> (bitmap of local_port, SPME index)}
- MPE is {(Local port, SMPE index) -> eVID}

In Spectrum-1, both indexes into the MPE table (local port and SMPE) are
derived from the PGT table. Therefore, the SMPE index needs to be
programmed as part of the PGT entry via new fields in SMID - 'smpe_valid'
and 'smpe'.

Add the two mentioned fields for future use and align the callers of
mlxsw_reg_smid2_pack() to pass zeros for SMPE fields.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Cohen 2022-06-19 13:29:13 +03:00 committed by David S. Miller
parent e0f071c5b8
commit 894b98d50b
2 changed files with 24 additions and 4 deletions
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21
drivers/net/ethernet/mellanox/mlxsw/reg.h
View File

@ -2198,6 +2198,23 @@ MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
*/
MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
/* reg_smid2_smpe_valid
* SMPE is valid.
* When not valid, the egress VID will not be modified by the SMPE table.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
/* reg_smid2_smpe
* Switch multicast port to egress VID.
* Access: RW
*
* Note: Reserved when legacy bridge model is used and on Spectrum-2.
*/
MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
/* reg_smid2_port
* Local port memebership (1 bit per port).
* Access: RW
@ -2211,13 +2228,15 @@ MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
bool set)
bool set, bool smpe_valid, u16 smpe)
{
MLXSW_REG_ZERO(smid2, payload);
mlxsw_reg_smid2_swid_set(payload, 0);
mlxsw_reg_smid2_mid_set(payload, mid);
mlxsw_reg_smid2_port_set(payload, port, set);
mlxsw_reg_smid2_port_mask_set(payload, port, 1);
mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid);
mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0);
}
/* CWTP - Congetion WRED ECN TClass Profile

7
drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c
View File

@ -887,7 +887,7 @@ static int mlxsw_sp_smid_router_port_set(struct mlxsw_sp *mlxsw_sp,
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx,
mlxsw_sp_router_port(mlxsw_sp), add);
mlxsw_sp_router_port(mlxsw_sp), add, false, 0);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);
kfree(smid2_pl);
return err;
@ -1584,7 +1584,7 @@ static int mlxsw_sp_port_smid_full_entry(struct mlxsw_sp *mlxsw_sp, u16 mid_idx,
if (!smid2_pl)
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, 0, false);
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, 0, false, false, 0);
for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) {
if (mlxsw_sp->ports[i])
mlxsw_reg_smid2_port_mask_set(smid2_pl, i, 1);
@ -1615,7 +1615,8 @@ static int mlxsw_sp_port_smid_set(struct mlxsw_sp_port *mlxsw_sp_port,
if (!smid2_pl)
return -ENOMEM;
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, mlxsw_sp_port->local_port, add);
mlxsw_reg_smid2_pack(smid2_pl, mid_idx, mlxsw_sp_port->local_port, add,
false, 0);
err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(smid2), smid2_pl);
kfree(smid2_pl);
return err;