regulator: rtmv20: Update DT binding document and property name parsing
1. Add vendor suffix to all proprietary properties. 2. Fix typo. 3. Change lsw to normal property, not pattern property. 4. Due to item 1, modify source code for property parsing. Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> Link: https://lore.kernel.org/r/1601460480-4259-1-git-send-email-u0084500@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
ChiYuan Huang
Mark Brown
parent
71d5f4dc7b
commit
89a5f77e3f
@ -26,108 +26,99 @@ properties:
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wakeup-source: true
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interrupts-extend:
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interrupts:
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maxItems: 1
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enable-gpios:
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description: A connection of the 'enable' gpio line.
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maxItems: 1
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ld-pulse-delay-us:
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richtek,ld-pulse-delay-us:
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description: |
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load current pulse delay in microsecond after strobe pin pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 100000
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default: 0
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ld-pulse-width-us:
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richtek,ld-pulse-width-us:
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description: |
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Load current pulse width in microsecond after strobe pin pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 10000
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default: 1200
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fsin1-delay-us:
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richtek,fsin1-delay-us:
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description: |
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Fsin1 pulse high delay in microsecond after vsync signal pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 100000
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default: 23000
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fsin1-width-us:
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richtek,fsin1-width-us:
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description: |
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Fsin1 pulse high width in microsecond after vsync signal pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 40
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maximum: 10000
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default: 160
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fsin2-delay-us:
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richtek,fsin2-delay-us:
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description: |
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Fsin2 pulse high delay in microsecond after vsync signal pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 100000
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default: 23000
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fsin2-width-us:
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richtek,fsin2-width-us:
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description: |
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Fsin2 pulse high width in microsecond after vsync signal pulse high.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 40
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maximum: 10000
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default: 160
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es-pulse-width-us:
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richtek,es-pulse-width-us:
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description: Eye safety function pulse width limit in microsecond.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 10000
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default: 1200
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es-ld-current-microamp:
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richtek,es-ld-current-microamp:
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description: Eye safety function load current limit in microamp.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 6000000
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default: 3000000
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lbp-level-microvolt:
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richtek,lbp-level-microvolt:
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description: Low battery protection level in microvolt.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 2400000
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maximum: 3700000
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default: 2700000
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lbp-enable:
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richtek,lbp-enable:
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description: Low battery protection function enable control.
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type: boolean
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strobe-polarity-high:
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richtek,strobe-polarity-high:
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description: Strobe pin active polarity control.
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type: boolean
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vsync-polarity-high:
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richtek,vsync-polarity-high:
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description: Vsync pin active polarity control.
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type: boolean
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fsin-enable:
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richtek,fsin-enable:
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description: Fsin function enable control.
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type: boolean
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fsin-output:
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richtek,fsin-output:
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description: Fsin function output control.
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type: boolean
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es-enable:
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richtek,es-enable:
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description: Eye safety function enable control.
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type: boolean
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patternProperties:
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"lsw":
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lsw:
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description: load switch current regulator description.
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type: object
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$ref: "regulator.yaml#"
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@ -135,7 +126,7 @@ required:
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- compatible
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- reg
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- wakeup-source
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- interrupts-extend
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- interrupts
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- enable-gpios
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- lsw
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@ -152,11 +143,11 @@ examples:
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compatible = "richtek,rtmv20";
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reg = <0x34>;
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wakeup-source;
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interrupts-extend = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>;
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interrupts-extended = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>;
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enable-gpios = <&gpio26 3 0>;
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strobe-polarity-high;
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vsync-polarity-high;
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richtek,strobe-polarity-high;
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richtek,vsync-polarity-high;
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lsw {
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regulator-name = "rtmv20,lsw";
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@ -166,28 +166,32 @@ static int rtmv20_properties_init(struct rtmv20_priv *priv)
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u32 addr;
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u32 mask;
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} props[] = {
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{ "ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
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{ "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
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RTMV20_DELAY_MASK },
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{ "ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
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{ "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
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RTMV20_WIDTH_MASK },
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{ "fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
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{ "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
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RTMV20_DELAY_MASK },
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{ "fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, RTMV20_WIDTH2_MASK },
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{ "fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
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{ "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3,
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RTMV20_WIDTH2_MASK },
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{ "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
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RTMV20_DELAY_MASK },
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{ "fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, RTMV20_WIDTH2_MASK },
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{ "es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
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{ "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3,
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RTMV20_WIDTH2_MASK },
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{ "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
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RTMV20_WIDTH_MASK },
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{ "es-ld-current-microamp", 3000000, 0, 6000000, 30000, RTMV20_REG_ESLDCTRL1,
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RTMV20_LDCURR_MASK },
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{ "lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
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{ "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000,
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RTMV20_REG_ESLDCTRL1, RTMV20_LDCURR_MASK },
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{ "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
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RTMV20_LBPLVL_MASK },
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{ "lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
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{ "strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_STROBEPOL_MASK },
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{ "vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_VSYNPOL_MASK },
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{ "fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
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{ "fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
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{ "es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
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{ "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
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{ "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
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RTMV20_STROBEPOL_MASK },
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{ "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
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RTMV20_VSYNPOL_MASK },
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{ "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
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{ "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
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{ "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
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};
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int i, ret;
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