Reset controller updates for v5.19
Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC reset controller support to reset-simple, and R9A07G054 USBPHY reset controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to device_reset(), simplify the uniphier-glue reset driver using bulk API and devres and clean up its dt-bindings docs. Convert most dt-bindings docs from txt to yaml. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCYnFPRRcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwOdpAP997XLr1A1I78UFSA8PPrGeL2Zy PFjyqq7nd0PXxZfIqQD7B0dkHR8p4oDerjSlKofsZiIw8Drf32E1O+F07gQFGgs= =0BLP -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJzzz0ACgkQmmx57+YA GNnhFA/7B2q3RAO2+TsxBVNXocg2qx4Bp+/GD0mInc/TdRZDmvlgOzFca+YElrOL amBYZITbNvTlFIKaQkVHmg1IMlGFTH4lCE9s41Jv2CbcN6/7+DcIGTYc21o3xj4P hbg3u1Ku9rlOvPrHoFaTrmg+5pgSeqt+sUaRReAOjoEIeb58hDlpDDxp1iXDGpSl eL1Ntjr9A5roERmponXWEWdh4TeI2YM62NGtH/y4d/HI7YDzovYeDgmOEZhqiQAy vICdSRGqqq8Bo+R0e4mQLKfc6SyyImA6jArpNrsmjtrubyUgcUCpytzmJNAknr7u +vnY4PjpaPai57lah1U2FmL+VZRHDlZ6GhCUeC5mYWGpWzQuc3t8VLDcyuCNlYTg xzMO4utZox8rQYVPfqAbJd86pszt0ph8b4gnxnZgpeBx7r816TJVM8nXmEMTY3/H K/6GEepGi6tslUh6X3bxjjqOzkF9z29iBqchOmll6rE+cGBAKmPpubjkSE5WczBN +fmjAmP3HQL7Vb/7qenKnpgU+M8Ypk3Mwlx2Y1bOkjPBoH3YQQ3BSFB0YUrzKdeC bSOM2yuNm9tBQeA8B6poYUmS5aCceLCNc0vov518yJcGxmPXokL45eWE6FCDUryD v8AmnYXtBXJUfiozcYTfsb9puZBDCEMspMP+6B1XyUdMmswErrE= =hOUj -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/drivers Reset controller updates for v5.19 Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC reset controller support to reset-simple, and R9A07G054 USBPHY reset controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to device_reset(), simplify the uniphier-glue reset driver using bulk API and devres and clean up its dt-bindings docs. Convert most dt-bindings docs from txt to yaml. * tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux: dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml dt-bindings: reset: lantiq,reset: Convert to yaml dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml dt-bindings: reset: berlin: Convert to yaml dt-bindings: reset: ath79: Convert to yaml dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L reset: ACPI reset support reset: simple: Add AST2600 compatible reset: reset-meson: add support for the Meson-S4 SoC Reset Controller dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller dt-bindings: reset: Add compatible for Meson-S4 Reset Controller reset: uniphier-glue: Use devm_add_action_or_reset() reset: uniphier-glue: Use reset_control_bulk API Link: https://lore.kernel.org/r/20220503160057.46625-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
89c500b1fa
47
Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
Normal file
47
Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/altr,rst-mgr.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: Altera SOCFPGA Reset Manager
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Dinh Nguyen <dinguyen@altera.com>
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
oneOf:
|
||||||
|
- description: Cyclone5/Arria5/Arria10
|
||||||
|
const: altr,rst-mgr
|
||||||
|
- description: Stratix10 ARM64 SoC
|
||||||
|
items:
|
||||||
|
- const: altr,stratix10-rst-mgr
|
||||||
|
- const: altr,rst-mgr
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
altr,modrst-offset:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
description: Offset of the first modrst register
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- altr,modrst-offset
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
rstmgr@ffd05000 {
|
||||||
|
compatible = "altr,rst-mgr";
|
||||||
|
reg = <0xffd05000 0x1000>;
|
||||||
|
altr,modrst-offset = <0x10>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
@ -1,22 +0,0 @@
|
|||||||
* Amlogic audio memory arbiter controller
|
|
||||||
|
|
||||||
The Amlogic Audio ARB is a simple device which enables or
|
|
||||||
disables the access of Audio FIFOs to DDR on AXG based SoC.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: 'amlogic,meson-axg-audio-arb' or
|
|
||||||
'amlogic,meson-sm1-audio-arb'
|
|
||||||
- reg: physical base address of the controller and length of memory
|
|
||||||
mapped region.
|
|
||||||
- clocks: phandle to the fifo peripheral clock provided by the audio
|
|
||||||
clock controller.
|
|
||||||
- #reset-cells: must be 1.
|
|
||||||
|
|
||||||
Example on the A113 SoC:
|
|
||||||
|
|
||||||
arb: reset-controller@280 {
|
|
||||||
compatible = "amlogic,meson-axg-audio-arb";
|
|
||||||
reg = <0x0 0x280 0x0 0x4>;
|
|
||||||
#reset-cells = <1>;
|
|
||||||
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
|
|
||||||
};
|
|
||||||
@ -0,0 +1,56 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
# Copyright 2019 BayLibre, SAS
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"
|
||||||
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||||
|
|
||||||
|
title: Amlogic audio memory arbiter controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Jerome Brunet <jbrunet@baylibre.com>
|
||||||
|
|
||||||
|
description: The Amlogic Audio ARB is a simple device which enables or disables
|
||||||
|
the access of Audio FIFOs to DDR on AXG based SoC.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
enum:
|
||||||
|
- amlogic,meson-axg-audio-arb
|
||||||
|
- amlogic,meson-sm1-audio-arb
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
clocks:
|
||||||
|
maxItems: 1
|
||||||
|
description: |
|
||||||
|
phandle to the fifo peripheral clock provided by the audio clock
|
||||||
|
controller.
|
||||||
|
|
||||||
|
"#reset-cells":
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- clocks
|
||||||
|
- "#reset-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
// on the A113 SoC:
|
||||||
|
#include <dt-bindings/clock/axg-audio-clkc.h>
|
||||||
|
bus {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
arb: reset-controller@280 {
|
||||||
|
compatible = "amlogic,meson-axg-audio-arb";
|
||||||
|
reg = <0x0 0x280 0x0 0x4>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
|
||||||
|
};
|
||||||
|
};
|
||||||
@ -17,6 +17,7 @@ properties:
|
|||||||
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
|
- amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
|
||||||
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
|
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
|
||||||
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
|
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
|
||||||
|
- amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
|
||||||
|
|
||||||
reg:
|
reg:
|
||||||
maxItems: 1
|
maxItems: 1
|
||||||
|
|||||||
@ -1,20 +0,0 @@
|
|||||||
Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
|
|
||||||
|
|
||||||
Please also refer to reset.txt in this directory for common reset
|
|
||||||
controller binding usage.
|
|
||||||
|
|
||||||
Required Properties:
|
|
||||||
- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
|
|
||||||
as fallback
|
|
||||||
- reg: Base address and size of the controllers memory area
|
|
||||||
- #reset-cells : Specifies the number of cells needed to encode reset
|
|
||||||
line, should be 1
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
reset-controller@1806001c {
|
|
||||||
compatible = "qca,ar9132-reset", "qca,ar7100-reset";
|
|
||||||
reg = <0x1806001c 0x4>;
|
|
||||||
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
@ -1,23 +0,0 @@
|
|||||||
Marvell Berlin reset controller
|
|
||||||
===============================
|
|
||||||
|
|
||||||
Please also refer to reset.txt in this directory for common reset
|
|
||||||
controller binding usage.
|
|
||||||
|
|
||||||
The reset controller node must be a sub-node of the chip controller
|
|
||||||
node on Berlin SoCs.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: should be "marvell,berlin2-reset"
|
|
||||||
- #reset-cells: must be set to 2
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
chip_rst: reset {
|
|
||||||
compatible = "marvell,berlin2-reset";
|
|
||||||
#reset-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
&usb_phy0 {
|
|
||||||
resets = <&chip_rst 0x104 12>;
|
|
||||||
};
|
|
||||||
@ -1,18 +0,0 @@
|
|||||||
Bitmain BM1880 SoC Reset Controller
|
|
||||||
===================================
|
|
||||||
|
|
||||||
Please also refer to reset.txt in this directory for common reset
|
|
||||||
controller binding usage.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: Should be "bitmain,bm1880-reset"
|
|
||||||
- reg: Offset and length of reset controller space in SCTRL.
|
|
||||||
- #reset-cells: Must be 1.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
rst: reset-controller@c00 {
|
|
||||||
compatible = "bitmain,bm1880-reset";
|
|
||||||
reg = <0xc00 0x8>;
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
@ -0,0 +1,36 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
# Copyright 2019 Manivannan Sadhasivam <mani@kernel.org>
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: "http://devicetree.org/schemas/reset/bitmain,bm1880-reset.yaml#"
|
||||||
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||||
|
|
||||||
|
title: Bitmain BM1880 SoC Reset Controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Manivannan Sadhasivam <mani@kernel.org>
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: bitmain,bm1880-reset
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
"#reset-cells":
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- "#reset-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
rst: reset-controller@c00 {
|
||||||
|
compatible = "bitmain,bm1880-reset";
|
||||||
|
reg = <0xc00 0x8>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
@ -1,30 +0,0 @@
|
|||||||
Lantiq XWAY SoC RCU reset controller binding
|
|
||||||
============================================
|
|
||||||
|
|
||||||
This binding describes a reset-controller found on the RCU module on Lantiq
|
|
||||||
XWAY SoCs.
|
|
||||||
|
|
||||||
This node has to be a sub node of the Lantiq RCU block.
|
|
||||||
|
|
||||||
-------------------------------------------------------------------------------
|
|
||||||
Required properties:
|
|
||||||
- compatible : Should be one of
|
|
||||||
"lantiq,danube-reset"
|
|
||||||
"lantiq,xrx200-reset"
|
|
||||||
- reg : Defines the following sets of registers in the parent
|
|
||||||
syscon device
|
|
||||||
- Offset of the reset set register
|
|
||||||
- Offset of the reset status register
|
|
||||||
- #reset-cells : Specifies the number of cells needed to encode the
|
|
||||||
reset line, should be 2.
|
|
||||||
The first cell takes the reset set bit and the
|
|
||||||
second cell takes the status bit.
|
|
||||||
|
|
||||||
-------------------------------------------------------------------------------
|
|
||||||
Example for the reset-controllers on the xRX200 SoCs:
|
|
||||||
reset0: reset-controller@10 {
|
|
||||||
compatible = "lantiq,xrx200-reset";
|
|
||||||
reg <0x10 0x04>, <0x14 0x04>;
|
|
||||||
|
|
||||||
#reset-cells = <2>;
|
|
||||||
};
|
|
||||||
49
Documentation/devicetree/bindings/reset/lantiq,reset.yaml
Normal file
49
Documentation/devicetree/bindings/reset/lantiq,reset.yaml
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: Lantiq XWAY SoC RCU reset controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
This binding describes a reset-controller found on the RCU module on Lantiq
|
||||||
|
XWAY SoCs. This node has to be a sub node of the Lantiq RCU block.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
enum:
|
||||||
|
- lantiq,danube-reset
|
||||||
|
- lantiq,xrx200-reset
|
||||||
|
|
||||||
|
reg:
|
||||||
|
description: |
|
||||||
|
Defines the following sets of registers in the parent syscon device
|
||||||
|
Offset of the reset set register
|
||||||
|
Offset of the reset status register
|
||||||
|
maxItems: 2
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
description: |
|
||||||
|
The first cell takes the reset set bit and the second cell takes the
|
||||||
|
status bit.
|
||||||
|
const: 2
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
// On the xRX200 SoCs:
|
||||||
|
reset0: reset-controller@10 {
|
||||||
|
compatible = "lantiq,xrx200-reset";
|
||||||
|
reg = <0x10 0x04>, <0x14 0x04>;
|
||||||
|
#reset-cells = <2>;
|
||||||
|
};
|
||||||
@ -0,0 +1,38 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
# Copyright 2015 Antoine Tenart <atenart@kernel.org>
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: "http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#"
|
||||||
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||||
|
|
||||||
|
title: Marvell Berlin reset controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Antoine Tenart <atenart@kernel.org>
|
||||||
|
|
||||||
|
description: The reset controller node must be a sub-node of the chip
|
||||||
|
controller node on Berlin SoCs.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: marvell,berlin2-reset
|
||||||
|
|
||||||
|
"#reset-cells":
|
||||||
|
const: 2
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- "#reset-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
chip: chip-control@ea0000 {
|
||||||
|
reg = <0xea0000 0x400>;
|
||||||
|
|
||||||
|
chip_rst: reset {
|
||||||
|
compatible = "marvell,berlin2-reset";
|
||||||
|
#reset-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
@ -1,32 +0,0 @@
|
|||||||
Nuvoton NPCM Reset controller
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
|
|
||||||
- reg : specifies physical base address and size of the register.
|
|
||||||
- #reset-cells: must be set to 2
|
|
||||||
|
|
||||||
Optional property:
|
|
||||||
- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
|
|
||||||
NPCM7xx contain four software reset that represent numbers 1 to 4.
|
|
||||||
|
|
||||||
If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
rstc: rstc@f0801000 {
|
|
||||||
compatible = "nuvoton,npcm750-reset";
|
|
||||||
reg = <0xf0801000 0x70>;
|
|
||||||
#reset-cells = <2>;
|
|
||||||
nuvoton,sw-reset-number = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
Specifying reset lines connected to IP NPCM7XX modules
|
|
||||||
======================================================
|
|
||||||
example:
|
|
||||||
|
|
||||||
spi0: spi@..... {
|
|
||||||
...
|
|
||||||
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
|
|
||||||
...
|
|
||||||
};
|
|
||||||
|
|
||||||
The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
|
|
||||||
@ -0,0 +1,50 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: Nuvoton NPCM Reset controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Tomer Maimon <tmaimon77@gmail.com>
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: nuvoton,npcm750-reset
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
const: 2
|
||||||
|
|
||||||
|
nuvoton,sw-reset-number:
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
minimum: 1
|
||||||
|
maximum: 4
|
||||||
|
description: |
|
||||||
|
Contains the software reset number to restart the SoC.
|
||||||
|
If not specified, software reset is disabled.
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
|
||||||
|
rstc: rstc@f0801000 {
|
||||||
|
compatible = "nuvoton,npcm750-reset";
|
||||||
|
reg = <0xf0801000 0x70>;
|
||||||
|
#reset-cells = <2>;
|
||||||
|
nuvoton,sw-reset-number = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Specifying reset lines connected to IP NPCM7XX modules
|
||||||
|
spi0: spi {
|
||||||
|
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
|
||||||
|
};
|
||||||
@ -0,0 +1,40 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
# Copyright 2015 Alban Bedel <albeu@free.fr>
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: "http://devicetree.org/schemas/reset/qca,ar7100-reset.yaml#"
|
||||||
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||||
|
|
||||||
|
title: Qualcomm Atheros AR7xxx/AR9XXX reset controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Alban Bedel <albeu@free.fr>
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
items:
|
||||||
|
- enum:
|
||||||
|
- qca,ar9132-reset
|
||||||
|
- qca,ar9331-reset
|
||||||
|
- const: qca,ar7100-reset
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
"#reset-cells":
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- "#reset-cells"
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
reset-controller@1806001c {
|
||||||
|
compatible = "qca,ar9132-reset", "qca,ar7100-reset";
|
||||||
|
reg = <0x1806001c 0x4>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
@ -1,33 +0,0 @@
|
|||||||
Binding for the AXS10x reset controller
|
|
||||||
|
|
||||||
This binding describes the ARC AXS10x boards custom IP-block which allows
|
|
||||||
to control reset signals of selected peripherals. For example DW GMAC, etc...
|
|
||||||
This block is controlled via memory-mapped register (AKA CREG) which
|
|
||||||
represents up-to 32 reset lines.
|
|
||||||
|
|
||||||
As of today only the following lines are used:
|
|
||||||
- DW GMAC - line 5
|
|
||||||
|
|
||||||
This binding uses the common reset binding[1].
|
|
||||||
|
|
||||||
[1] Documentation/devicetree/bindings/reset/reset.txt
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: should be "snps,axs10x-reset".
|
|
||||||
- reg: should always contain pair address - length: for creg reset
|
|
||||||
bits register.
|
|
||||||
- #reset-cells: from common reset binding; Should always be set to 1.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
reset: reset-controller@11220 {
|
|
||||||
compatible = "snps,axs10x-reset";
|
|
||||||
#reset-cells = <1>;
|
|
||||||
reg = <0x11220 0x4>;
|
|
||||||
};
|
|
||||||
|
|
||||||
Specifying reset lines connected to IP modules:
|
|
||||||
ethernet@.... {
|
|
||||||
....
|
|
||||||
resets = <&reset 5>;
|
|
||||||
....
|
|
||||||
};
|
|
||||||
@ -0,0 +1,48 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: AXS10x reset controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
This binding describes the ARC AXS10x boards custom IP-block which allows
|
||||||
|
to control reset signals of selected peripherals. For example DW GMAC, etc...
|
||||||
|
This block is controlled via memory-mapped register (AKA CREG) which
|
||||||
|
represents up-to 32 reset lines.
|
||||||
|
As of today only the following lines are used:
|
||||||
|
- DW GMAC - line 5
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: snps,axs10x-reset
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
reset: reset-controller@11220 {
|
||||||
|
compatible = "snps,axs10x-reset";
|
||||||
|
#reset-cells = <1>;
|
||||||
|
reg = <0x11220 0x4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Specifying reset lines connected to IP modules:
|
||||||
|
ethernet {
|
||||||
|
resets = <&reset 5>;
|
||||||
|
};
|
||||||
@ -1,16 +0,0 @@
|
|||||||
Altera SOCFPGA Reset Manager
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
|
|
||||||
"altr,stratix10-rst-mgr","altr,rst-mgr" for Stratix10 ARM64 SoC
|
|
||||||
- reg : Should contain 1 register ranges(address and length)
|
|
||||||
- altr,modrst-offset : Should contain the offset of the first modrst register.
|
|
||||||
- #reset-cells: 1
|
|
||||||
|
|
||||||
Example:
|
|
||||||
rstmgr@ffd05000 {
|
|
||||||
#reset-cells = <1>;
|
|
||||||
compatible = "altr,rst-mgr";
|
|
||||||
reg = <0xffd05000 0x1000>;
|
|
||||||
altr,modrst-offset = <0x10>;
|
|
||||||
};
|
|
||||||
@ -38,25 +38,49 @@ properties:
|
|||||||
minItems: 1
|
minItems: 1
|
||||||
maxItems: 2
|
maxItems: 2
|
||||||
|
|
||||||
clock-names:
|
clock-names: true
|
||||||
oneOf:
|
|
||||||
- items: # for Pro4, Pro5
|
|
||||||
- const: gio
|
|
||||||
- const: link
|
|
||||||
- items: # for others
|
|
||||||
- const: link
|
|
||||||
|
|
||||||
resets:
|
resets:
|
||||||
minItems: 1
|
minItems: 1
|
||||||
maxItems: 2
|
maxItems: 2
|
||||||
|
|
||||||
reset-names:
|
reset-names: true
|
||||||
oneOf:
|
|
||||||
- items: # for Pro4, Pro5
|
allOf:
|
||||||
- const: gio
|
- if:
|
||||||
- const: link
|
properties:
|
||||||
- items: # for others
|
compatible:
|
||||||
- const: link
|
contains:
|
||||||
|
enum:
|
||||||
|
- socionext,uniphier-pro4-usb3-reset
|
||||||
|
- socionext,uniphier-pro5-usb3-reset
|
||||||
|
- socionext,uniphier-pro4-ahci-reset
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
clocks:
|
||||||
|
minItems: 2
|
||||||
|
maxItems: 2
|
||||||
|
clock-names:
|
||||||
|
items:
|
||||||
|
- const: gio
|
||||||
|
- const: link
|
||||||
|
resets:
|
||||||
|
minItems: 2
|
||||||
|
maxItems: 2
|
||||||
|
reset-names:
|
||||||
|
items:
|
||||||
|
- const: gio
|
||||||
|
- const: link
|
||||||
|
else:
|
||||||
|
properties:
|
||||||
|
clocks:
|
||||||
|
maxItems: 1
|
||||||
|
clock-names:
|
||||||
|
const: link
|
||||||
|
resets:
|
||||||
|
maxItems: 1
|
||||||
|
reset-names:
|
||||||
|
const: link
|
||||||
|
|
||||||
additionalProperties: false
|
additionalProperties: false
|
||||||
|
|
||||||
|
|||||||
@ -1,42 +0,0 @@
|
|||||||
STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
|
|
||||||
=============================================================================
|
|
||||||
|
|
||||||
This binding describes a reset controller device that is used to enable and
|
|
||||||
disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
|
|
||||||
the STi family SoC system configuration registers.
|
|
||||||
|
|
||||||
The actual action taken when softreset is asserted is hardware dependent.
|
|
||||||
However, when asserted it may not be possible to access the hardware's
|
|
||||||
registers and after an assert/deassert sequence the hardware's previous state
|
|
||||||
may no longer be valid.
|
|
||||||
|
|
||||||
Please refer to Documentation/devicetree/bindings/reset/reset.txt
|
|
||||||
for common reset controller binding usage.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: Should be "st,stih407-picophyreset"
|
|
||||||
- #reset-cells: 1, see below
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
picophyreset: picophyreset-controller {
|
|
||||||
compatible = "st,stih407-picophyreset";
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
Specifying picophyreset control of devices
|
|
||||||
=======================================
|
|
||||||
|
|
||||||
Device nodes should specify the reset channel required in their "resets"
|
|
||||||
property, containing a phandle to the picophyreset device node and an
|
|
||||||
index specifying which channel to use, as described in
|
|
||||||
Documentation/devicetree/bindings/reset/reset.txt.
|
|
||||||
|
|
||||||
Example:
|
|
||||||
|
|
||||||
usb2_picophy0: usbpicophy@0 {
|
|
||||||
resets = <&picophyreset STIH407_PICOPHY0_RESET>;
|
|
||||||
};
|
|
||||||
|
|
||||||
Macro definitions for the supported reset channels can be found in:
|
|
||||||
include/dt-bindings/reset/stih407-resets.h
|
|
||||||
@ -1,45 +0,0 @@
|
|||||||
STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
|
|
||||||
=============================================================================
|
|
||||||
|
|
||||||
This binding describes a reset controller device that is used to enable and
|
|
||||||
disable on-chip peripheral controllers such as USB and SATA, using
|
|
||||||
"powerdown" control bits found in the STi family SoC system configuration
|
|
||||||
registers. These have been grouped together into a single reset controller
|
|
||||||
device for convenience.
|
|
||||||
|
|
||||||
The actual action taken when powerdown is asserted is hardware dependent.
|
|
||||||
However, when asserted it may not be possible to access the hardware's
|
|
||||||
registers and after an assert/deassert sequence the hardware's previous state
|
|
||||||
may no longer be valid.
|
|
||||||
|
|
||||||
Please refer to reset.txt in this directory for common reset
|
|
||||||
controller binding usage.
|
|
||||||
|
|
||||||
Required properties:
|
|
||||||
- compatible: Should be "st,stih407-powerdown"
|
|
||||||
- #reset-cells: 1, see below
|
|
||||||
|
|
||||||
example:
|
|
||||||
|
|
||||||
powerdown: powerdown-controller {
|
|
||||||
compatible = "st,stih407-powerdown";
|
|
||||||
#reset-cells = <1>;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
Specifying powerdown control of devices
|
|
||||||
=======================================
|
|
||||||
|
|
||||||
Device nodes should specify the reset channel required in their "resets"
|
|
||||||
property, containing a phandle to the powerdown device node and an
|
|
||||||
index specifying which channel to use, as described in reset.txt
|
|
||||||
|
|
||||||
example:
|
|
||||||
|
|
||||||
st_dwc3: dwc3@8f94000 {
|
|
||||||
resets = <&powerdown STIH407_USB3_POWERDOWN>,
|
|
||||||
};
|
|
||||||
|
|
||||||
Macro definitions for the supported reset channels can be found in:
|
|
||||||
|
|
||||||
include/dt-bindings/reset/stih407-resets.h
|
|
||||||
@ -0,0 +1,47 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Peter Griffin <peter.griffin@linaro.org>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
This binding describes a reset controller device that is used to enable and
|
||||||
|
disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
|
||||||
|
the STi family SoC system configuration registers.
|
||||||
|
|
||||||
|
The actual action taken when softreset is asserted is hardware dependent.
|
||||||
|
However, when asserted it may not be possible to access the hardware's
|
||||||
|
registers and after an assert/deassert sequence the hardware's previous state
|
||||||
|
may no longer be valid.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: st,stih407-picophyreset
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/reset/stih407-resets.h>
|
||||||
|
|
||||||
|
picophyreset: picophyreset-controller {
|
||||||
|
compatible = "st,stih407-picophyreset";
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Specifying picophyreset control of devices
|
||||||
|
usb2_picophy0: usbpicophy {
|
||||||
|
resets = <&picophyreset STIH407_PICOPHY0_RESET>;
|
||||||
|
};
|
||||||
@ -0,0 +1,49 @@
|
|||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Srinivas Kandagatla <srinivas.kandagatla@st.com>
|
||||||
|
|
||||||
|
description: |
|
||||||
|
This binding describes a reset controller device that is used to enable and
|
||||||
|
disable on-chip peripheral controllers such as USB and SATA, using
|
||||||
|
"powerdown" control bits found in the STi family SoC system configuration
|
||||||
|
registers. These have been grouped together into a single reset controller
|
||||||
|
device for convenience.
|
||||||
|
|
||||||
|
The actual action taken when powerdown is asserted is hardware dependent.
|
||||||
|
However, when asserted it may not be possible to access the hardware's
|
||||||
|
registers and after an assert/deassert sequence the hardware's previous state
|
||||||
|
may no longer be valid.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: st,stih407-powerdown
|
||||||
|
|
||||||
|
'#reset-cells':
|
||||||
|
const: 1
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- '#reset-cells'
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/reset/stih407-resets.h>
|
||||||
|
|
||||||
|
powerdown: powerdown-controller {
|
||||||
|
compatible = "st,stih407-powerdown";
|
||||||
|
#reset-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
// Specifying powerdown control of devices:
|
||||||
|
st_dwc3: dwc3 {
|
||||||
|
resets = <&powerdown STIH407_USB3_POWERDOWN>;
|
||||||
|
};
|
||||||
@ -183,7 +183,7 @@ config RESET_RASPBERRYPI
|
|||||||
|
|
||||||
config RESET_RZG2L_USBPHY_CTRL
|
config RESET_RZG2L_USBPHY_CTRL
|
||||||
tristate "Renesas RZ/G2L USBPHY control driver"
|
tristate "Renesas RZ/G2L USBPHY control driver"
|
||||||
depends on ARCH_R9A07G044 || COMPILE_TEST
|
depends on ARCH_RZG2L || COMPILE_TEST
|
||||||
help
|
help
|
||||||
Support for USBPHY Control found on RZ/G2L family. It mainly
|
Support for USBPHY Control found on RZ/G2L family. It mainly
|
||||||
controls reset and power down of the USB/PHY.
|
controls reset and power down of the USB/PHY.
|
||||||
|
|||||||
@ -12,6 +12,7 @@
|
|||||||
#include <linux/kref.h>
|
#include <linux/kref.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
|
#include <linux/acpi.h>
|
||||||
#include <linux/reset.h>
|
#include <linux/reset.h>
|
||||||
#include <linux/reset-controller.h>
|
#include <linux/reset-controller.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
@ -1100,13 +1101,25 @@ EXPORT_SYMBOL_GPL(__devm_reset_control_bulk_get);
|
|||||||
*
|
*
|
||||||
* Convenience wrapper for __reset_control_get() and reset_control_reset().
|
* Convenience wrapper for __reset_control_get() and reset_control_reset().
|
||||||
* This is useful for the common case of devices with single, dedicated reset
|
* This is useful for the common case of devices with single, dedicated reset
|
||||||
* lines.
|
* lines. _RST firmware method will be called for devices with ACPI.
|
||||||
*/
|
*/
|
||||||
int __device_reset(struct device *dev, bool optional)
|
int __device_reset(struct device *dev, bool optional)
|
||||||
{
|
{
|
||||||
struct reset_control *rstc;
|
struct reset_control *rstc;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
#ifdef CONFIG_ACPI
|
||||||
|
acpi_handle handle = ACPI_HANDLE(dev);
|
||||||
|
|
||||||
|
if (handle) {
|
||||||
|
if (!acpi_has_method(handle, "_RST"))
|
||||||
|
return optional ? 0 : -ENOENT;
|
||||||
|
if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL,
|
||||||
|
NULL)))
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
rstc = __reset_control_get(dev, NULL, 0, 0, optional, true);
|
rstc = __reset_control_get(dev, NULL, 0, 0, optional, true);
|
||||||
if (IS_ERR(rstc))
|
if (IS_ERR(rstc))
|
||||||
return PTR_ERR(rstc);
|
return PTR_ERR(rstc);
|
||||||
|
|||||||
@ -98,11 +98,17 @@ static const struct meson_reset_param meson_a1_param = {
|
|||||||
.level_offset = 0x40,
|
.level_offset = 0x40,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct meson_reset_param meson_s4_param = {
|
||||||
|
.reg_count = 6,
|
||||||
|
.level_offset = 0x40,
|
||||||
|
};
|
||||||
|
|
||||||
static const struct of_device_id meson_reset_dt_ids[] = {
|
static const struct of_device_id meson_reset_dt_ids[] = {
|
||||||
{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
|
{ .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
|
||||||
{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
|
{ .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
|
||||||
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
|
{ .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
|
||||||
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
|
{ .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
|
||||||
|
{ .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param},
|
||||||
{ /* sentinel */ },
|
{ /* sentinel */ },
|
||||||
};
|
};
|
||||||
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
|
MODULE_DEVICE_TABLE(of, meson_reset_dt_ids);
|
||||||
|
|||||||
@ -144,6 +144,7 @@ static const struct of_device_id reset_simple_dt_ids[] = {
|
|||||||
.data = &reset_simple_active_low },
|
.data = &reset_simple_active_low },
|
||||||
{ .compatible = "aspeed,ast2400-lpc-reset" },
|
{ .compatible = "aspeed,ast2400-lpc-reset" },
|
||||||
{ .compatible = "aspeed,ast2500-lpc-reset" },
|
{ .compatible = "aspeed,ast2500-lpc-reset" },
|
||||||
|
{ .compatible = "aspeed,ast2600-lpc-reset" },
|
||||||
{ .compatible = "bitmain,bm1880-reset",
|
{ .compatible = "bitmain,bm1880-reset",
|
||||||
.data = &reset_simple_active_low },
|
.data = &reset_simple_active_low },
|
||||||
{ .compatible = "brcm,bcm4908-misc-pcie-reset",
|
{ .compatible = "brcm,bcm4908-misc-pcie-reset",
|
||||||
|
|||||||
@ -23,19 +23,32 @@ struct uniphier_glue_reset_soc_data {
|
|||||||
|
|
||||||
struct uniphier_glue_reset_priv {
|
struct uniphier_glue_reset_priv {
|
||||||
struct clk_bulk_data clk[MAX_CLKS];
|
struct clk_bulk_data clk[MAX_CLKS];
|
||||||
struct reset_control *rst[MAX_RSTS];
|
struct reset_control_bulk_data rst[MAX_RSTS];
|
||||||
struct reset_simple_data rdata;
|
struct reset_simple_data rdata;
|
||||||
const struct uniphier_glue_reset_soc_data *data;
|
const struct uniphier_glue_reset_soc_data *data;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static void uniphier_clk_disable(void *_priv)
|
||||||
|
{
|
||||||
|
struct uniphier_glue_reset_priv *priv = _priv;
|
||||||
|
|
||||||
|
clk_bulk_disable_unprepare(priv->data->nclks, priv->clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void uniphier_rst_assert(void *_priv)
|
||||||
|
{
|
||||||
|
struct uniphier_glue_reset_priv *priv = _priv;
|
||||||
|
|
||||||
|
reset_control_bulk_assert(priv->data->nrsts, priv->rst);
|
||||||
|
}
|
||||||
|
|
||||||
static int uniphier_glue_reset_probe(struct platform_device *pdev)
|
static int uniphier_glue_reset_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
struct device *dev = &pdev->dev;
|
struct device *dev = &pdev->dev;
|
||||||
struct uniphier_glue_reset_priv *priv;
|
struct uniphier_glue_reset_priv *priv;
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
resource_size_t size;
|
resource_size_t size;
|
||||||
const char *name;
|
int i, ret;
|
||||||
int i, ret, nr;
|
|
||||||
|
|
||||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||||
if (!priv)
|
if (!priv)
|
||||||
@ -58,22 +71,28 @@ static int uniphier_glue_reset_probe(struct platform_device *pdev)
|
|||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
for (i = 0; i < priv->data->nrsts; i++) {
|
for (i = 0; i < priv->data->nrsts; i++)
|
||||||
name = priv->data->reset_names[i];
|
priv->rst[i].id = priv->data->reset_names[i];
|
||||||
priv->rst[i] = devm_reset_control_get_shared(dev, name);
|
ret = devm_reset_control_bulk_get_shared(dev, priv->data->nrsts,
|
||||||
if (IS_ERR(priv->rst[i]))
|
priv->rst);
|
||||||
return PTR_ERR(priv->rst[i]);
|
if (ret)
|
||||||
}
|
return ret;
|
||||||
|
|
||||||
ret = clk_bulk_prepare_enable(priv->data->nclks, priv->clk);
|
ret = clk_bulk_prepare_enable(priv->data->nclks, priv->clk);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
for (nr = 0; nr < priv->data->nrsts; nr++) {
|
ret = devm_add_action_or_reset(dev, uniphier_clk_disable, priv);
|
||||||
ret = reset_control_deassert(priv->rst[nr]);
|
if (ret)
|
||||||
if (ret)
|
return ret;
|
||||||
goto out_rst_assert;
|
|
||||||
}
|
ret = reset_control_bulk_deassert(priv->data->nrsts, priv->rst);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = devm_add_action_or_reset(dev, uniphier_rst_assert, priv);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
spin_lock_init(&priv->rdata.lock);
|
spin_lock_init(&priv->rdata.lock);
|
||||||
priv->rdata.rcdev.owner = THIS_MODULE;
|
priv->rdata.rcdev.owner = THIS_MODULE;
|
||||||
@ -84,32 +103,7 @@ static int uniphier_glue_reset_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
platform_set_drvdata(pdev, priv);
|
platform_set_drvdata(pdev, priv);
|
||||||
|
|
||||||
ret = devm_reset_controller_register(dev, &priv->rdata.rcdev);
|
return devm_reset_controller_register(dev, &priv->rdata.rcdev);
|
||||||
if (ret)
|
|
||||||
goto out_rst_assert;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
out_rst_assert:
|
|
||||||
while (nr--)
|
|
||||||
reset_control_assert(priv->rst[nr]);
|
|
||||||
|
|
||||||
clk_bulk_disable_unprepare(priv->data->nclks, priv->clk);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int uniphier_glue_reset_remove(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct uniphier_glue_reset_priv *priv = platform_get_drvdata(pdev);
|
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < priv->data->nrsts; i++)
|
|
||||||
reset_control_assert(priv->rst[i]);
|
|
||||||
|
|
||||||
clk_bulk_disable_unprepare(priv->data->nclks, priv->clk);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const char * const uniphier_pro4_clock_reset_names[] = {
|
static const char * const uniphier_pro4_clock_reset_names[] = {
|
||||||
@ -177,7 +171,6 @@ MODULE_DEVICE_TABLE(of, uniphier_glue_reset_match);
|
|||||||
|
|
||||||
static struct platform_driver uniphier_glue_reset_driver = {
|
static struct platform_driver uniphier_glue_reset_driver = {
|
||||||
.probe = uniphier_glue_reset_probe,
|
.probe = uniphier_glue_reset_probe,
|
||||||
.remove = uniphier_glue_reset_remove,
|
|
||||||
.driver = {
|
.driver = {
|
||||||
.name = "uniphier-glue-reset",
|
.name = "uniphier-glue-reset",
|
||||||
.of_match_table = uniphier_glue_reset_match,
|
.of_match_table = uniphier_glue_reset_match,
|
||||||
|
|||||||
125
include/dt-bindings/reset/amlogic,meson-s4-reset.h
Normal file
125
include/dt-bindings/reset/amlogic,meson-s4-reset.h
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
|
||||||
|
* Author: Zelong Dong <zelong.dong@amlogic.com>
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
|
||||||
|
#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H
|
||||||
|
|
||||||
|
/* RESET0 */
|
||||||
|
#define RESET_USB_DDR0 0
|
||||||
|
#define RESET_USB_DDR1 1
|
||||||
|
#define RESET_USB_DDR2 2
|
||||||
|
#define RESET_USB_DDR3 3
|
||||||
|
#define RESET_USBCTRL 4
|
||||||
|
/* 5-7 */
|
||||||
|
#define RESET_USBPHY20 8
|
||||||
|
#define RESET_USBPHY21 9
|
||||||
|
/* 10-15 */
|
||||||
|
#define RESET_HDMITX_APB 16
|
||||||
|
#define RESET_BRG_VCBUS_DEC 17
|
||||||
|
#define RESET_VCBUS 18
|
||||||
|
#define RESET_VID_PLL_DIV 19
|
||||||
|
#define RESET_VDI6 20
|
||||||
|
#define RESET_GE2D 21
|
||||||
|
#define RESET_HDMITXPHY 22
|
||||||
|
#define RESET_VID_LOCK 23
|
||||||
|
#define RESET_VENCL 24
|
||||||
|
#define RESET_VDAC 25
|
||||||
|
#define RESET_VENCP 26
|
||||||
|
#define RESET_VENCI 27
|
||||||
|
#define RESET_RDMA 28
|
||||||
|
#define RESET_HDMI_TX 29
|
||||||
|
#define RESET_VIU 30
|
||||||
|
#define RESET_VENC 31
|
||||||
|
|
||||||
|
/* RESET1 */
|
||||||
|
#define RESET_AUDIO 32
|
||||||
|
#define RESET_MALI_APB 33
|
||||||
|
#define RESET_MALI 34
|
||||||
|
#define RESET_DDR_APB 35
|
||||||
|
#define RESET_DDR 36
|
||||||
|
#define RESET_DOS_APB 37
|
||||||
|
#define RESET_DOS 38
|
||||||
|
/* 39-47 */
|
||||||
|
#define RESET_ETH 48
|
||||||
|
/* 49-51 */
|
||||||
|
#define RESET_DEMOD 52
|
||||||
|
/* 53-63 */
|
||||||
|
|
||||||
|
/* RESET2 */
|
||||||
|
#define RESET_ABUS_ARB 64
|
||||||
|
#define RESET_IR_CTRL 65
|
||||||
|
#define RESET_TEMPSENSOR_DDR 66
|
||||||
|
#define RESET_TEMPSENSOR_PLL 67
|
||||||
|
/* 68-71 */
|
||||||
|
#define RESET_SMART_CARD 72
|
||||||
|
#define RESET_SPICC0 73
|
||||||
|
/* 74 */
|
||||||
|
#define RESET_RSA 75
|
||||||
|
/* 76-79 */
|
||||||
|
#define RESET_MSR_CLK 80
|
||||||
|
#define RESET_SPIFC 81
|
||||||
|
#define RESET_SARADC 82
|
||||||
|
/* 83-87 */
|
||||||
|
#define RESET_ACODEC 88
|
||||||
|
#define RESET_CEC 89
|
||||||
|
#define RESET_AFIFO 90
|
||||||
|
#define RESET_WATCHDOG 91
|
||||||
|
/* 92-95 */
|
||||||
|
|
||||||
|
/* RESET3 */
|
||||||
|
/* 96-127 */
|
||||||
|
|
||||||
|
/* RESET4 */
|
||||||
|
/* 128-131 */
|
||||||
|
#define RESET_PWM_AB 132
|
||||||
|
#define RESET_PWM_CD 133
|
||||||
|
#define RESET_PWM_EF 134
|
||||||
|
#define RESET_PWM_GH 135
|
||||||
|
#define RESET_PWM_IJ 136
|
||||||
|
/* 137 */
|
||||||
|
#define RESET_UART_A 138
|
||||||
|
#define RESET_UART_B 139
|
||||||
|
#define RESET_UART_C 140
|
||||||
|
#define RESET_UART_D 141
|
||||||
|
#define RESET_UART_E 142
|
||||||
|
/* 143 */
|
||||||
|
#define RESET_I2C_S_A 144
|
||||||
|
#define RESET_I2C_M_A 145
|
||||||
|
#define RESET_I2C_M_B 146
|
||||||
|
#define RESET_I2C_M_C 147
|
||||||
|
#define RESET_I2C_M_D 148
|
||||||
|
#define RESET_I2C_M_E 149
|
||||||
|
/* 150-151 */
|
||||||
|
#define RESET_SD_EMMC_A 152
|
||||||
|
#define RESET_SD_EMMC_B 153
|
||||||
|
#define RESET_NAND_EMMC 154
|
||||||
|
/* 155-159 */
|
||||||
|
|
||||||
|
/* RESET5 */
|
||||||
|
#define RESET_BRG_VDEC_PIPL0 160
|
||||||
|
#define RESET_BRG_HEVCF_PIPL0 161
|
||||||
|
/* 162 */
|
||||||
|
#define RESET_BRG_HCODEC_PIPL0 163
|
||||||
|
#define RESET_BRG_GE2D_PIPL0 164
|
||||||
|
#define RESET_BRG_VPU_PIPL0 165
|
||||||
|
#define RESET_BRG_CPU_PIPL0 166
|
||||||
|
#define RESET_BRG_MALI_PIPL0 167
|
||||||
|
/* 168 */
|
||||||
|
#define RESET_BRG_MALI_PIPL1 169
|
||||||
|
/* 170-171 */
|
||||||
|
#define RESET_BRG_HEVCF_PIPL1 172
|
||||||
|
#define RESET_BRG_HEVCB_PIPL1 173
|
||||||
|
/* 174-183 */
|
||||||
|
#define RESET_RAMA 184
|
||||||
|
/* 185-186 */
|
||||||
|
#define RESET_BRG_NIC_VAPB 187
|
||||||
|
#define RESET_BRG_NIC_DSU 188
|
||||||
|
#define RESET_BRG_NIC_SYSCLK 189
|
||||||
|
#define RESET_BRG_NIC_MAIN 190
|
||||||
|
#define RESET_BRG_NIC_ALL 191
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user