ASoC: fsl_micfil: Driver updates
Merge series from Sascha Hauer <s.hauer@pengutronix.de>: Cleanups for the fsl_micfil driver.
This commit is contained in:
Mark Brown
commit
89d2bce7e6
@ -25,7 +25,7 @@
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#include <linux/of_dma.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include "dmaengine.h"
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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@ -14,6 +14,7 @@
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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@ -35,7 +36,7 @@
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#include <linux/workqueue.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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@ -73,6 +74,7 @@
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#define SDMA_CHNENBL0_IMX35 0x200
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#define SDMA_CHNENBL0_IMX31 0x080
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#define SDMA_CHNPRI_0 0x100
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#define SDMA_DONE0_CONFIG 0x1000
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/*
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* Buffer descriptor status values.
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@ -180,6 +182,12 @@
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BIT(DMA_MEM_TO_DEV) | \
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BIT(DMA_DEV_TO_DEV))
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#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
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#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
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#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
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#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
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/**
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* struct sdma_script_start_addrs - SDMA script start pointers
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*
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@ -441,6 +449,9 @@ struct sdma_channel {
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struct work_struct terminate_worker;
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struct list_head terminated;
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bool is_ram_script;
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unsigned int n_fifos_src;
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unsigned int n_fifos_dst;
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bool sw_done;
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};
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#define IMX_DMA_SG_LOOP BIT(0)
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@ -778,6 +789,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
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val = readl_relaxed(sdma->regs + chnenbl);
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__set_bit(channel, &val);
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writel_relaxed(val, sdma->regs + chnenbl);
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/* Set SDMA_DONEx_CONFIG is sw_done enabled */
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if (sdmac->sw_done) {
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val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
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val |= SDMA_DONE0_CONFIG_DONE_SEL;
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val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
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writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
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}
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}
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static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
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@ -940,7 +959,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
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/*
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* sets the pc of SDMA script according to the peripheral type
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*/
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static void sdma_get_pc(struct sdma_channel *sdmac,
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static int sdma_get_pc(struct sdma_channel *sdmac,
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enum sdma_peripheral_type peripheral_type)
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{
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struct sdma_engine *sdma = sdmac->sdma;
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@ -1038,14 +1057,22 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
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case IMX_DMATYPE_IPU_MEMORY:
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emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
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break;
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default:
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case IMX_DMATYPE_MULTI_SAI:
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per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
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emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
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break;
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default:
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dev_err(sdma->dev, "Unsupported transfer type %d\n",
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peripheral_type);
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return -EINVAL;
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}
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sdmac->pc_from_device = per_2_emi;
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sdmac->pc_to_device = emi_2_per;
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sdmac->device_to_device = per_2_per;
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sdmac->pc_to_pc = emi_2_emi;
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return 0;
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}
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static int sdma_load_context(struct sdma_channel *sdmac)
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@ -1210,9 +1237,26 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
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sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
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}
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static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
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{
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unsigned int n_fifos;
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if (sdmac->sw_done)
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sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
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if (sdmac->direction == DMA_DEV_TO_MEM)
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n_fifos = sdmac->n_fifos_src;
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else
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n_fifos = sdmac->n_fifos_dst;
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sdmac->watermark_level |=
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FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos);
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}
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static int sdma_config_channel(struct dma_chan *chan)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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int ret;
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sdma_disable_channel(chan);
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@ -1233,7 +1277,9 @@ static int sdma_config_channel(struct dma_chan *chan)
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break;
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}
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sdma_get_pc(sdmac, sdmac->peripheral_type);
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ret = sdma_get_pc(sdmac, sdmac->peripheral_type);
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if (ret)
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return ret;
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if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
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(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
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@ -1243,6 +1289,10 @@ static int sdma_config_channel(struct dma_chan *chan)
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sdmac->peripheral_type == IMX_DMATYPE_ASRC)
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sdma_set_watermarklevel_for_p2p(sdmac);
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} else {
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if (sdmac->peripheral_type ==
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IMX_DMATYPE_MULTI_SAI)
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sdma_set_watermarklevel_for_sais(sdmac);
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__set_bit(sdmac->event_id0, sdmac->event_mask);
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}
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@ -1349,7 +1399,9 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
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mem_data.dma_request2 = 0;
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data = &mem_data;
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sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
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ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
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if (ret)
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return ret;
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}
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switch (data->priority) {
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@ -1698,9 +1750,23 @@ static int sdma_config(struct dma_chan *chan,
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struct dma_slave_config *dmaengine_cfg)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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struct sdma_engine *sdma = sdmac->sdma;
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memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
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if (dmaengine_cfg->peripheral_config) {
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struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
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if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
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dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
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dmaengine_cfg->peripheral_size,
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sizeof(struct sdma_peripheral_config));
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return -EINVAL;
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}
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sdmac->n_fifos_src = sdmacfg->n_fifos_src;
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sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
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sdmac->sw_done = sdmacfg->sw_done;
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}
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/* Set ENBLn earlier to make sure dma request triggered after that */
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if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
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return -EINVAL;
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@ -39,7 +39,7 @@
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#include <asm/irq.h>
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#include <linux/platform_data/mmc-mxcmmc.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#define DRIVER_NAME "mxc-mmc"
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#define MXCMCI_TIMEOUT_MS 10000
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@ -20,7 +20,7 @@
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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@ -24,7 +24,7 @@
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#include <linux/of_device.h>
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#include <linux/property.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#define DRIVER_NAME "spi_imx"
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@ -30,7 +30,7 @@
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include "serial_mctrl_gpio.h"
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@ -26,7 +26,7 @@
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#include <linux/dma/ipu-dma.h>
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#include <linux/backlight.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include <linux/platform_data/video-mx3fb.h>
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#include <asm/io.h>
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@ -3,8 +3,8 @@
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __ASM_ARCH_MXC_DMA_H__
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#define __ASM_ARCH_MXC_DMA_H__
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#ifndef __LINUX_DMA_IMX_H
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#define __LINUX_DMA_IMX_H
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#include <linux/scatterlist.h>
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#include <linux/device.h>
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@ -39,6 +39,7 @@ enum sdma_peripheral_type {
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IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
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IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
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IMX_DMATYPE_SAI, /* SAI */
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IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
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};
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enum imx_dma_prio {
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@ -65,4 +66,23 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
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!strcmp(chan->device->dev->driver->name, "imx-dma");
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}
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#endif
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/**
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* struct sdma_peripheral_config - SDMA config for audio
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* @n_fifos_src: Number of FIFOs for recording
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* @n_fifos_dst: Number of FIFOs for playback
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* @sw_done: Use software done. Needed for PDM (micfil)
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*
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* Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
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* registers. For multichannel recording/playback the SAI/micfil have
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* one FIFO register per channel and the SDMA engine has to read/write
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* the next channel from/to the next register and wrap around to the
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* first register when all channels are handled. The number of active
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* channels must be communicated to the SDMA engine using this struct.
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*/
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struct sdma_peripheral_config {
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int n_fifos_src;
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int n_fifos_dst;
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bool sw_done;
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};
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#endif /* __LINUX_DMA_IMX_H */
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@ -11,7 +11,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include <linux/pm_runtime.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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@ -8,7 +8,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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@ -7,7 +7,7 @@
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#define _FSL_EASRC_H
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#include <sound/asound.h>
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#include <linux/platform_data/dma-imx.h>
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#include <linux/dma/imx-dma.h>
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#include "fsl_asrc_common.h"
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright 2018 NXP
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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@ -15,6 +16,7 @@
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#include <linux/regmap.h>
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#include <linux/sysfs.h>
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#include <linux/types.h>
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#include <linux/dma/imx-dma.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm.h>
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#include <sound/soc.h>
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@ -22,10 +24,17 @@
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#include <sound/core.h>
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#include "fsl_micfil.h"
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#include "imx-pcm.h"
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#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
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#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
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#define MICFIL_OSR_DEFAULT 16
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enum quality {
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QUALITY_HIGH,
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QUALITY_MEDIUM,
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QUALITY_LOW,
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QUALITY_VLOW0,
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QUALITY_VLOW1,
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QUALITY_VLOW2,
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};
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struct fsl_micfil {
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struct platform_device *pdev;
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@ -34,13 +43,11 @@ struct fsl_micfil {
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struct clk *busclk;
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struct clk *mclk;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct sdma_peripheral_config sdmacfg;
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unsigned int dataline;
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char name[32];
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int irq[MICFIL_IRQ_LINES];
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unsigned int mclk_streams;
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int quality; /*QUALITY 2-0 bits */
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bool slave_mode;
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int channel_gain[8];
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enum quality quality;
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};
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struct fsl_micfil_soc_data {
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@ -63,29 +70,73 @@ static const struct of_device_id fsl_micfil_dt_ids[] = {
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};
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MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
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/* Table 5. Quality Modes
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* Medium 0 0 0
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* High 0 0 1
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* Very Low 2 1 0 0
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* Very Low 1 1 0 1
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* Very Low 0 1 1 0
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* Low 1 1 1
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*/
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static const char * const micfil_quality_select_texts[] = {
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"Medium", "High",
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"N/A", "N/A",
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"VLow2", "VLow1",
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"VLow0", "Low",
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[QUALITY_HIGH] = "High",
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[QUALITY_MEDIUM] = "Medium",
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[QUALITY_LOW] = "Low",
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[QUALITY_VLOW0] = "VLow0",
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[QUALITY_VLOW1] = "Vlow1",
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[QUALITY_VLOW2] = "Vlow2",
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};
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static const struct soc_enum fsl_micfil_quality_enum =
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SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
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MICFIL_CTRL2_QSEL_SHIFT,
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ARRAY_SIZE(micfil_quality_select_texts),
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micfil_quality_select_texts);
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
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micfil_quality_select_texts);
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static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
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static int micfil_set_quality(struct fsl_micfil *micfil)
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{
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u32 qsel;
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switch (micfil->quality) {
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case QUALITY_HIGH:
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qsel = MICFIL_QSEL_HIGH_QUALITY;
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break;
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case QUALITY_MEDIUM:
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qsel = MICFIL_QSEL_MEDIUM_QUALITY;
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break;
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case QUALITY_LOW:
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qsel = MICFIL_QSEL_LOW_QUALITY;
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break;
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case QUALITY_VLOW0:
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qsel = MICFIL_QSEL_VLOW0_QUALITY;
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break;
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case QUALITY_VLOW1:
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qsel = MICFIL_QSEL_VLOW1_QUALITY;
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break;
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case QUALITY_VLOW2:
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qsel = MICFIL_QSEL_VLOW2_QUALITY;
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break;
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}
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return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
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MICFIL_CTRL2_QSEL,
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FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
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}
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static int micfil_quality_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
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ucontrol->value.integer.value[0] = micfil->quality;
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||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int micfil_quality_set(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
|
||||
struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
|
||||
|
||||
micfil->quality = ucontrol->value.integer.value[0];
|
||||
|
||||
return micfil_set_quality(micfil);
|
||||
}
|
||||
|
||||
static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
|
||||
SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
|
||||
MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
|
||||
@ -105,64 +156,9 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
|
||||
MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
|
||||
SOC_ENUM_EXT("MICFIL Quality Select",
|
||||
fsl_micfil_quality_enum,
|
||||
snd_soc_get_enum_double, snd_soc_put_enum_double),
|
||||
micfil_quality_get, micfil_quality_set),
|
||||
};
|
||||
|
||||
static inline int get_pdm_clk(struct fsl_micfil *micfil,
|
||||
unsigned int rate)
|
||||
{
|
||||
u32 ctrl2_reg;
|
||||
int qsel, osr;
|
||||
int bclk;
|
||||
|
||||
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
|
||||
osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
|
||||
>> MICFIL_CTRL2_CICOSR_SHIFT);
|
||||
|
||||
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
|
||||
qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
|
||||
|
||||
switch (qsel) {
|
||||
case MICFIL_HIGH_QUALITY:
|
||||
bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
|
||||
break;
|
||||
case MICFIL_MEDIUM_QUALITY:
|
||||
case MICFIL_VLOW0_QUALITY:
|
||||
bclk = rate * 4 * osr * 1; /* kfactor = 1 */
|
||||
break;
|
||||
case MICFIL_LOW_QUALITY:
|
||||
case MICFIL_VLOW1_QUALITY:
|
||||
bclk = rate * 2 * osr * 2; /* kfactor = 2 */
|
||||
break;
|
||||
case MICFIL_VLOW2_QUALITY:
|
||||
bclk = rate * osr * 4; /* kfactor = 4 */
|
||||
break;
|
||||
default:
|
||||
dev_err(&micfil->pdev->dev,
|
||||
"Please make sure you select a valid quality.\n");
|
||||
bclk = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
return bclk;
|
||||
}
|
||||
|
||||
static inline int get_clk_div(struct fsl_micfil *micfil,
|
||||
unsigned int rate)
|
||||
{
|
||||
u32 ctrl2_reg;
|
||||
long mclk_rate;
|
||||
int clk_div;
|
||||
|
||||
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
|
||||
|
||||
mclk_rate = clk_get_rate(micfil->mclk);
|
||||
|
||||
clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
|
||||
|
||||
return clk_div;
|
||||
}
|
||||
|
||||
/* The SRES is a self-negated bit which provides the CPU with the
|
||||
* capability to initialize the PDM Interface module through the
|
||||
* slave-bus interface. This bit always reads as zero, and this
|
||||
@ -173,45 +169,19 @@ static int fsl_micfil_reset(struct device *dev)
|
||||
struct fsl_micfil *micfil = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = regmap_update_bits(micfil->regmap,
|
||||
REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_MDIS_MASK,
|
||||
0);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
|
||||
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_MDIS);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(micfil->regmap,
|
||||
REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_SRES_MASK,
|
||||
MICFIL_CTRL1_SRES);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
|
||||
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_SRES);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
|
||||
unsigned int freq)
|
||||
{
|
||||
struct device *dev = &micfil->pdev->dev;
|
||||
int ret;
|
||||
|
||||
clk_disable_unprepare(micfil->mclk);
|
||||
|
||||
ret = clk_set_rate(micfil->mclk, freq * 1024);
|
||||
if (ret)
|
||||
dev_warn(dev, "failed to set rate (%u): %d\n",
|
||||
freq * 1024, ret);
|
||||
|
||||
clk_prepare_enable(micfil->mclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_micfil_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
@ -249,42 +219,32 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
* 11 - reserved
|
||||
*/
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_DISEL_MASK,
|
||||
(1 << MICFIL_CTRL1_DISEL_SHIFT));
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to update DISEL bits\n");
|
||||
MICFIL_CTRL1_DISEL,
|
||||
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable the module */
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN_MASK,
|
||||
MICFIL_CTRL1_PDMIEN);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable the module\n");
|
||||
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
/* Disable the module */
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN_MASK,
|
||||
0);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable the module\n");
|
||||
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_DISEL_MASK,
|
||||
(0 << MICFIL_CTRL1_DISEL_SHIFT));
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to update DISEL bits\n");
|
||||
MICFIL_CTRL1_DISEL,
|
||||
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
@ -292,39 +252,6 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_set_clock_params(struct device *dev, unsigned int rate)
|
||||
{
|
||||
struct fsl_micfil *micfil = dev_get_drvdata(dev);
|
||||
int clk_div;
|
||||
int ret;
|
||||
|
||||
ret = fsl_micfil_set_mclk_rate(micfil, rate);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
|
||||
clk_get_rate(micfil->mclk), rate);
|
||||
|
||||
/* set CICOSR */
|
||||
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
|
||||
MICFIL_CTRL2_CICOSR_MASK,
|
||||
MICFIL_CTRL2_OSR_DEFAULT);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
|
||||
REG_MICFIL_CTRL2);
|
||||
|
||||
/* set CLK_DIV */
|
||||
clk_div = get_clk_div(micfil, rate);
|
||||
if (clk_div < 0)
|
||||
ret = -EINVAL;
|
||||
|
||||
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
|
||||
MICFIL_CTRL2_CLKDIV_MASK, clk_div);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
|
||||
REG_MICFIL_CTRL2);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
@ -332,97 +259,69 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
|
||||
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
|
||||
unsigned int channels = params_channels(params);
|
||||
unsigned int rate = params_rate(params);
|
||||
struct device *dev = &micfil->pdev->dev;
|
||||
int clk_div = 8;
|
||||
int osr = MICFIL_OSR_DEFAULT;
|
||||
int ret;
|
||||
|
||||
/* 1. Disable the module */
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN_MASK, 0);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to disable the module\n");
|
||||
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
MICFIL_CTRL1_PDMIEN);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable channels */
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
|
||||
0xFF, ((1 << channels) - 1));
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
|
||||
REG_MICFIL_CTRL1);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fsl_set_clock_params(dev, rate);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
|
||||
ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = micfil_set_quality(micfil);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
|
||||
MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
|
||||
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
|
||||
FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
|
||||
|
||||
micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
|
||||
micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
|
||||
micfil->sdmacfg.n_fifos_src = channels;
|
||||
micfil->sdmacfg.sw_done = true;
|
||||
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
|
||||
unsigned int freq, int dir)
|
||||
{
|
||||
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
|
||||
struct device *dev = &micfil->pdev->dev;
|
||||
|
||||
int ret;
|
||||
|
||||
if (!freq)
|
||||
return 0;
|
||||
|
||||
ret = fsl_micfil_set_mclk_rate(micfil, freq);
|
||||
if (ret < 0)
|
||||
dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
|
||||
clk_get_rate(micfil->mclk), freq);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
|
||||
.startup = fsl_micfil_startup,
|
||||
.trigger = fsl_micfil_trigger,
|
||||
.hw_params = fsl_micfil_hw_params,
|
||||
.set_sysclk = fsl_micfil_set_dai_sysclk,
|
||||
};
|
||||
|
||||
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
|
||||
{
|
||||
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
|
||||
struct device *dev = cpu_dai->dev;
|
||||
unsigned int val;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* set qsel to medium */
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
|
||||
MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
|
||||
REG_MICFIL_CTRL2);
|
||||
return ret;
|
||||
}
|
||||
micfil->quality = QUALITY_MEDIUM;
|
||||
|
||||
/* set default gain to max_gain */
|
||||
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
|
||||
for (i = 0; i < 8; i++)
|
||||
micfil->channel_gain[i] = 0xF;
|
||||
|
||||
snd_soc_dai_init_dma_data(cpu_dai, NULL,
|
||||
&micfil->dma_params_rx);
|
||||
|
||||
/* FIFO Watermark Control - FIFOWMK*/
|
||||
val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
|
||||
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
|
||||
MICFIL_FIFO_CTRL_FIFOWMK_MASK,
|
||||
val);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set FIFOWMK\n");
|
||||
MICFIL_FIFO_CTRL_FIFOWMK,
|
||||
FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -433,8 +332,8 @@ static struct snd_soc_dai_driver fsl_micfil_dai = {
|
||||
.stream_name = "CPU-Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 8,
|
||||
.rates = FSL_MICFIL_RATES,
|
||||
.formats = FSL_MICFIL_FORMATS,
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.ops = &fsl_micfil_dai_ops,
|
||||
};
|
||||
@ -578,11 +477,11 @@ static irqreturn_t micfil_isr(int irq, void *devid)
|
||||
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
|
||||
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
|
||||
|
||||
dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
|
||||
dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
|
||||
|
||||
/* Channel 0-7 Output Data Flags */
|
||||
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
|
||||
if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
|
||||
if (stat_reg & MICFIL_STAT_CHXF(i))
|
||||
dev_dbg(&pdev->dev,
|
||||
"Data available in Data Channel %d\n", i);
|
||||
/* if DMA is not enabled, field must be written with 1
|
||||
@ -591,17 +490,17 @@ static irqreturn_t micfil_isr(int irq, void *devid)
|
||||
if (!dma_enabled)
|
||||
regmap_write_bits(micfil->regmap,
|
||||
REG_MICFIL_STAT,
|
||||
MICFIL_STAT_CHXF_MASK(i),
|
||||
MICFIL_STAT_CHXF(i),
|
||||
1);
|
||||
}
|
||||
|
||||
for (i = 0; i < MICFIL_FIFO_NUM; i++) {
|
||||
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
|
||||
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
|
||||
dev_dbg(&pdev->dev,
|
||||
"FIFO Overflow Exception flag for channel %d\n",
|
||||
i);
|
||||
|
||||
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
|
||||
if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
|
||||
dev_dbg(&pdev->dev,
|
||||
"FIFO Underflow Exception flag for channel %d\n",
|
||||
i);
|
||||
@ -618,16 +517,16 @@ static irqreturn_t micfil_err_isr(int irq, void *devid)
|
||||
|
||||
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
|
||||
|
||||
if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
|
||||
if (stat_reg & MICFIL_STAT_BSY_FIL)
|
||||
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
|
||||
|
||||
if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
|
||||
if (stat_reg & MICFIL_STAT_FIR_RDY)
|
||||
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
|
||||
|
||||
if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
|
||||
if (stat_reg & MICFIL_STAT_LOWFREQF) {
|
||||
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
|
||||
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
|
||||
MICFIL_STAT_LOWFREQF_MASK, 1);
|
||||
MICFIL_STAT_LOWFREQF, 1);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
@ -640,7 +539,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
|
||||
struct resource *res;
|
||||
void __iomem *regs;
|
||||
int ret, i;
|
||||
unsigned long irqflag = 0;
|
||||
|
||||
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
|
||||
if (!micfil)
|
||||
@ -699,17 +597,13 @@ static int fsl_micfil_probe(struct platform_device *pdev)
|
||||
/* get IRQs */
|
||||
for (i = 0; i < MICFIL_IRQ_LINES; i++) {
|
||||
micfil->irq[i] = platform_get_irq(pdev, i);
|
||||
dev_err(&pdev->dev, "GET IRQ: %d\n", micfil->irq[i]);
|
||||
if (micfil->irq[i] < 0)
|
||||
return micfil->irq[i];
|
||||
}
|
||||
|
||||
if (of_property_read_bool(np, "fsl,shared-interrupt"))
|
||||
irqflag = IRQF_SHARED;
|
||||
|
||||
/* Digital Microphone interface interrupt */
|
||||
ret = devm_request_irq(&pdev->dev, micfil->irq[0],
|
||||
micfil_isr, irqflag,
|
||||
micfil_isr, IRQF_SHARED,
|
||||
micfil->name, micfil);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
|
||||
@ -719,7 +613,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
|
||||
|
||||
/* Digital Microphone interface error interrupt */
|
||||
ret = devm_request_irq(&pdev->dev, micfil->irq[1],
|
||||
micfil_err_isr, irqflag,
|
||||
micfil_err_isr, IRQF_SHARED,
|
||||
micfil->name, micfil);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
|
||||
@ -731,7 +625,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
|
||||
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
|
||||
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
|
||||
|
||||
|
||||
platform_set_drvdata(pdev, micfil);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
@ -33,240 +33,94 @@
|
||||
#define REG_MICFIL_VAD0_ZCD 0xA8
|
||||
|
||||
/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
|
||||
#define MICFIL_CTRL1_MDIS_SHIFT 31
|
||||
#define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
|
||||
#define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
|
||||
#define MICFIL_CTRL1_DOZEN_SHIFT 30
|
||||
#define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
|
||||
#define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
|
||||
#define MICFIL_CTRL1_PDMIEN_SHIFT 29
|
||||
#define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
|
||||
#define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
|
||||
#define MICFIL_CTRL1_DBG_SHIFT 28
|
||||
#define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
|
||||
#define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
|
||||
#define MICFIL_CTRL1_SRES_SHIFT 27
|
||||
#define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
|
||||
#define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
|
||||
#define MICFIL_CTRL1_DBGE_SHIFT 26
|
||||
#define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
|
||||
#define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
|
||||
#define MICFIL_CTRL1_DISEL_SHIFT 24
|
||||
#define MICFIL_CTRL1_DISEL_WIDTH 2
|
||||
#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
|
||||
<< MICFIL_CTRL1_DISEL_SHIFT)
|
||||
#define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
& MICFIL_CTRL1_DISEL_MASK)
|
||||
#define MICFIL_CTRL1_ERREN_SHIFT 23
|
||||
#define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
|
||||
#define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
|
||||
#define MICFIL_CTRL1_CHEN_SHIFT 0
|
||||
#define MICFIL_CTRL1_CHEN_WIDTH 8
|
||||
#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
|
||||
#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
|
||||
#define MICFIL_CTRL1_MDIS BIT(31)
|
||||
#define MICFIL_CTRL1_DOZEN BIT(30)
|
||||
#define MICFIL_CTRL1_PDMIEN BIT(29)
|
||||
#define MICFIL_CTRL1_DBG BIT(28)
|
||||
#define MICFIL_CTRL1_SRES BIT(27)
|
||||
#define MICFIL_CTRL1_DBGE BIT(26)
|
||||
|
||||
#define MICFIL_CTRL1_DISEL_DISABLE 0
|
||||
#define MICFIL_CTRL1_DISEL_DMA 1
|
||||
#define MICFIL_CTRL1_DISEL_IRQ 2
|
||||
#define MICFIL_CTRL1_DISEL GENMASK(25, 24)
|
||||
#define MICFIL_CTRL1_ERREN BIT(23)
|
||||
#define MICFIL_CTRL1_CHEN(ch) BIT(ch)
|
||||
|
||||
/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
|
||||
#define MICFIL_CTRL2_QSEL_SHIFT 25
|
||||
#define MICFIL_CTRL2_QSEL_WIDTH 3
|
||||
#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
|
||||
<< MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
|
||||
#define MICFIL_CTRL2_QSEL GENMASK(27, 25)
|
||||
#define MICFIL_QSEL_MEDIUM_QUALITY 0
|
||||
#define MICFIL_QSEL_HIGH_QUALITY 1
|
||||
#define MICFIL_QSEL_LOW_QUALITY 7
|
||||
#define MICFIL_QSEL_VLOW0_QUALITY 6
|
||||
#define MICFIL_QSEL_VLOW1_QUALITY 5
|
||||
#define MICFIL_QSEL_VLOW2_QUALITY 4
|
||||
|
||||
#define MICFIL_CTRL2_CICOSR_SHIFT 16
|
||||
#define MICFIL_CTRL2_CICOSR_WIDTH 4
|
||||
#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
|
||||
<< MICFIL_CTRL2_CICOSR_SHIFT)
|
||||
#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
|
||||
& MICFIL_CTRL2_CICOSR_MASK)
|
||||
#define MICFIL_CTRL2_CLKDIV_SHIFT 0
|
||||
#define MICFIL_CTRL2_CLKDIV_WIDTH 8
|
||||
#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
|
||||
<< MICFIL_CTRL2_CLKDIV_SHIFT)
|
||||
#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
|
||||
& MICFIL_CTRL2_CLKDIV_MASK)
|
||||
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
|
||||
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
|
||||
|
||||
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
|
||||
#define MICFIL_STAT_BSY_FIL_SHIFT 31
|
||||
#define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT)
|
||||
#define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT)
|
||||
#define MICFIL_STAT_FIR_RDY_SHIFT 30
|
||||
#define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
|
||||
#define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
|
||||
#define MICFIL_STAT_LOWFREQF_SHIFT 29
|
||||
#define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
|
||||
#define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
|
||||
#define MICFIL_STAT_CHXF_SHIFT(v) (v)
|
||||
#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
|
||||
#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
|
||||
#define MICFIL_STAT_BSY_FIL BIT(31)
|
||||
#define MICFIL_STAT_FIR_RDY BIT(30)
|
||||
#define MICFIL_STAT_LOWFREQF BIT(29)
|
||||
#define MICFIL_STAT_CHXF(ch) BIT(ch)
|
||||
|
||||
/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
|
||||
<< MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
|
||||
& MICFIL_FIFO_CTRL_FIFOWMK_MASK)
|
||||
#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
|
||||
|
||||
/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
|
||||
#define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v)
|
||||
#define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
|
||||
#define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
|
||||
#define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
|
||||
#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
|
||||
#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
|
||||
|
||||
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
|
||||
#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24
|
||||
#define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3
|
||||
#define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL1_CHSEL_MASK)
|
||||
#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16
|
||||
#define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4
|
||||
#define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL1_CICOSR_MASK)
|
||||
#define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
|
||||
#define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
|
||||
#define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL1_INITT_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL1_INITT_MASK)
|
||||
#define MICFIL_VAD0_CTRL1_ST10_SHIFT 4
|
||||
#define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3
|
||||
#define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_IE_SHIFT 2
|
||||
#define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_RST_SHIFT 1
|
||||
#define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_EN_SHIFT 0
|
||||
#define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
|
||||
#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
|
||||
#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
|
||||
#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
|
||||
#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
|
||||
#define MICFIL_VAD0_CTRL1_IE BIT(2)
|
||||
#define MICFIL_VAD0_CTRL1_RST BIT(1)
|
||||
#define MICFIL_VAD0_CTRL1_EN BIT(0)
|
||||
|
||||
/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
|
||||
#define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31
|
||||
#define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30
|
||||
#define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
|
||||
#define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
|
||||
#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
|
||||
#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL2_FRAMET_MASK)
|
||||
#define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
|
||||
#define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
|
||||
#define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL2_INPGAIN_MASK)
|
||||
#define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
|
||||
#define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
|
||||
#define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_CTRL2_HPF_SHIFT)
|
||||
#define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
|
||||
& MICFIL_VAD0_CTRL2_HPF_MASK)
|
||||
#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
|
||||
#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
|
||||
#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
|
||||
#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
|
||||
#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
|
||||
#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
|
||||
|
||||
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
|
||||
#define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31
|
||||
#define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
|
||||
#define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
|
||||
#define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30
|
||||
#define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
|
||||
#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
|
||||
#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
|
||||
#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
|
||||
#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
|
||||
#define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
|
||||
& MICFIL_VAD0_SCONFIG_SGAIN_MASK)
|
||||
#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
|
||||
#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
|
||||
#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
|
||||
|
||||
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
|
||||
#define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31
|
||||
#define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30
|
||||
#define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29
|
||||
#define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28
|
||||
#define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
|
||||
#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
|
||||
#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
|
||||
& MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
|
||||
#define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
|
||||
#define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
|
||||
#define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
|
||||
#define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
|
||||
& MICFIL_VAD0_NCONFIG_NGAIN_MASK)
|
||||
#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
|
||||
#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
|
||||
#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
|
||||
#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
|
||||
#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
|
||||
#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
|
||||
|
||||
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
|
||||
<< MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
|
||||
& MICFIL_VAD0_ZCD_ZCDTH_MASK)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
|
||||
<< MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
|
||||
& MICFIL_VAD0_ZCD_ZCDADJ_MASK)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4
|
||||
#define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2
|
||||
#define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0
|
||||
#define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
|
||||
#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
|
||||
#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
|
||||
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
|
||||
#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
|
||||
|
||||
/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
|
||||
#define MICFIL_VAD0_STAT_INITF_SHIFT 31
|
||||
#define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_INSATF_SHIFT 16
|
||||
#define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_EF_SHIFT 15
|
||||
#define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_IF_SHIFT 0
|
||||
#define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT)
|
||||
#define MICFIL_VAD0_STAT_INITF BIT(31)
|
||||
#define MICFIL_VAD0_STAT_INSATF BIT(16)
|
||||
#define MICFIL_VAD0_STAT_EF BIT(15)
|
||||
#define MICFIL_VAD0_STAT_IF BIT(0)
|
||||
|
||||
/* MICFIL Output Control Register */
|
||||
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
|
||||
|
||||
/* Constants */
|
||||
#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
|
||||
#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
|
||||
== ((v) & MICFIL_CTRL1_DISEL_MASK))
|
||||
#define MICFIL_OUTPUT_CHANNELS 8
|
||||
#define MICFIL_FIFO_NUM 8
|
||||
|
||||
@ -278,6 +132,5 @@
|
||||
#define MICFIL_SLEEP_MIN 90000 /* in us */
|
||||
#define MICFIL_SLEEP_MAX 100000 /* in us */
|
||||
#define MICFIL_DMA_MAXBURST_RX 6
|
||||
#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
|
||||
|
||||
#endif /* _FSL_MICFIL_H */
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#ifndef _IMX_PCM_H
|
||||
#define _IMX_PCM_H
|
||||
|
||||
#include <linux/platform_data/dma-imx.h>
|
||||
#include <linux/dma/imx-dma.h>
|
||||
|
||||
/*
|
||||
* Do not change this as the FIQ handler depends on this size
|
||||
|
||||
@ -182,7 +182,7 @@
|
||||
#define DRV_NAME "imx-ssi"
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/platform_data/dma-imx.h>
|
||||
#include <linux/dma/imx-dma.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include "imx-pcm.h"
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user