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[ARM] 4261/1: clockevent support for Versatile platform

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Update Versatile platform to use new clockevent infrastructure.

Signed-off-by: Kevin Hilman <khilman@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Kevin Hilman 2007-03-08 20:30:38 +01:00 committed by Russell King
parent b49c87c2a5
commit 89df127246
2 changed files with 59 additions and 10 deletions
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1
arch/arm/Kconfig
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@ -167,6 +167,7 @@ config ARCH_VERSATILE
select ARM_VIC select ARM_VIC
select ICST307 select ICST307
select GENERIC_TIME select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help help
This enables support for ARM Ltd Versatile board. This enables support for ARM Ltd Versatile board.

68
arch/arm/mach-versatile/core.c
View File

@ -27,6 +27,7 @@
#include <linux/amba/bus.h> #include <linux/amba/bus.h>
#include <linux/amba/clcd.h> #include <linux/amba/clcd.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <asm/cnt32_to_63.h> #include <asm/cnt32_to_63.h>
#include <asm/system.h> #include <asm/system.h>
@ -829,19 +830,61 @@ void __init versatile_init(void)
#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
#endif #endif
static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
unsigned long ctrl;
switch(mode) {
case CLOCK_EVT_MODE_PERIODIC:
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
ctrl = TIMER_CTRL_PERIODIC;
ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctrl = TIMER_CTRL_ONESHOT;
ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
ctrl = 0;
}
writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
}
static int timer_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
return 0;
}
static struct clock_event_device timer0_clockevent = {
.name = "timer0",
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = timer_set_mode,
.set_next_event = timer_set_next_event,
};
/* /*
* IRQ handler for the timer * IRQ handler for the timer
*/ */
static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id) static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
{ {
write_seqlock(&xtime_lock); struct clock_event_device *evt = &timer0_clockevent;
// ...clear the interrupt
writel(1, TIMER0_VA_BASE + TIMER_INTCLR); writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
timer_tick(); evt->event_handler(evt);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
@ -909,17 +952,22 @@ static void __init versatile_timer_init(void)
writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL);
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
/* /*
* Make irqs happen for the system timer * Make irqs happen for the system timer
*/ */
setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq); setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
versatile_clocksource_init(); versatile_clocksource_init();
timer0_clockevent.mult =
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&timer0_clockevent);
} }
struct sys_timer versatile_timer = { struct sys_timer versatile_timer = {