- Do not enable AMD memory encryption in Kconfig by default due to
shortcomings of some platforms, leading to boot failures. - Mask out invalid bits in the MXCSR for 32-bit kernels again because Thomas and I don't know how to mask out bits properly. Third time's the charm. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmFr8jgACgkQEsHwGGHe VUrdew//UzC9aVoDuhD/oyK5/rN24x6eipOjjhbFRNHZP6zcPE2+YXiWRk16JKUz wbQnJP+1MlU4K8swDoN+mqYAvl/SK48dOPGrknnLzMITV3HsfTr6X8wEAKfzSFH6 m25ElTzay4V10oHPSB2B6jOc9GRnMeA/dinfguzmGJfYHgr7dJ89weJ7F3gPP6Hj +q6g8lJaSJjtZMwweas/0vc6mLb5De6InoimVJQoX2bXcuczS7mou+1SSaaE9wNp /NnSzAPcbTYkY+2iEFM8hKWKxX/a3j0brJzvrxIw/ggcmoYSNm6Gvw2htjwoPhYs KlI8Wx2NTvfua93zleaad3131tnIqBgIfpC/7xhD+gYJanbn6p4ZlqrY74qrfPQ2 L15OUnBRFb9/I8zohke7FvjV8OPDJ7P3fp9QkeRp5wwIKSGunQ/AreWo3or+scpY eNP4DOUSOOObsgpQXbmOBphqnV9UpOtCQUcEaBH4PyF9G2H0KZQiSjD4DCDIiaBa aQjNlWoC5s89aQdHDGU4iouM5ldmfiT4F65OI2FEClm1/xyqdpMqM+Q0khZKnXow 5hSZitV5tRiR40M4wnE/3XoQt57OaFtwLs8K1InimZGOttgGhr//fsuwaGU0nL5l oQLg9FuwphRupeMz0a6KmzNcMG34rb1IE8q2twDq3BULi9c97L0= =dZ4h -----END PGP SIGNATURE----- Merge tag 'x86_urgent_for_v5.15_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: - Do not enable AMD memory encryption in Kconfig by default due to shortcomings of some platforms, leading to boot failures. - Mask out invalid bits in the MXCSR for 32-bit kernels again because Thomas and I don't know how to mask out bits properly. Third time's the charm. * tag 'x86_urgent_for_v5.15_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/fpu: Mask out the invalid MXCSR bits properly x86/Kconfig: Do not enable AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT automatically
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commit
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@ -1525,7 +1525,6 @@ config AMD_MEM_ENCRYPT
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config AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
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bool "Activate AMD Secure Memory Encryption (SME) by default"
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default y
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depends on AMD_MEM_ENCRYPT
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help
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Say yes to have system memory encrypted by default if running on
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@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx,
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return -EINVAL;
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} else {
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/* Mask invalid bits out for historical reasons (broken hardware). */
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fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask;
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fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
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}
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/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
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