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The biggest fix is the restoration of mmap ioctl for gen12 integrated parts

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which lack was breaking ADL-P with media stack.
 Besides that a small selftest fix and a theoretical overflow on
 i915->pipe_to_crtc_mapping.
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Merge tag 'drm-intel-next-fixes-2021-06-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

The biggest fix is the restoration of mmap ioctl for gen12 integrated parts
which lack was breaking ADL-P with media stack.
Besides that a small selftest fix and a theoretical overflow on
i915->pipe_to_crtc_mapping.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YNtsfguvCRSROBUZ@intel.com
This commit is contained in:
Dave Airlie 2021-06-30 15:42:01 +10:00
commit 8a02ea42bc
6 changed files with 76 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -9618,7 +9618,6 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
struct intel_crtc *slave, *master;
@ -9634,15 +9633,15 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
if (!new_crtc_state->bigjoiner)
return 0;
if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
slave = intel_dsc_get_bigjoiner_secondary(crtc);
if (!slave) {
DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
"CRTC + 1 to be used, doesn't exist\n",
crtc->base.base.id, crtc->base.name);
return -EINVAL;
}
slave = new_crtc_state->bigjoiner_linked_crtc =
intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
new_crtc_state->bigjoiner_linked_crtc = slave;
slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
master = crtc;
if (IS_ERR(slave_crtc_state))

8
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1723,6 +1723,14 @@ vlv_pipe_to_channel(enum pipe pipe)
}
}
static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
{
return (pipe >= 0 &&
pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
i915->pipe_to_crtc_mapping[pipe]);
}
static inline struct intel_crtc *
intel_get_first_crtc(struct drm_i915_private *dev_priv)
{

40
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -1106,6 +1106,27 @@ static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
}
static struct intel_crtc *
_get_crtc_for_pipe(struct drm_i915_private *i915, enum pipe pipe)
{
if (!intel_pipe_valid(i915, pipe))
return NULL;
return intel_get_crtc_for_pipe(i915, pipe);
}
struct intel_crtc *
intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc)
{
return _get_crtc_for_pipe(to_i915(primary_crtc->base.dev), primary_crtc->pipe + 1);
}
static struct intel_crtc *
intel_dsc_get_bigjoiner_primary(const struct intel_crtc *secondary_crtc)
{
return _get_crtc_for_pipe(to_i915(secondary_crtc->base.dev), secondary_crtc->pipe - 1);
}
void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@ -1178,15 +1199,13 @@ void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
crtc_state->bigjoiner = true;
if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
crtc_state->bigjoiner_linked_crtc =
intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
} else if (dss_ctl1 & UNCOMPRESSED_JOINER_SLAVE) {
crtc_state->bigjoiner = true;
crtc_state->bigjoiner_slave = true;
if (!WARN_ON(crtc->pipe == PIPE_A))
crtc_state->bigjoiner_linked_crtc =
intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);
drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
}
}
@ -1224,14 +1243,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
crtc_state->bigjoiner_slave = true;
if (!WARN_ON(crtc->pipe == PIPE_A))
crtc_state->bigjoiner_linked_crtc =
intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_primary(crtc);
} else {
if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
crtc_state->bigjoiner_linked_crtc =
intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
crtc_state->bigjoiner_linked_crtc = intel_dsc_get_bigjoiner_secondary(crtc);
}
drm_WARN_ON(&dev_priv->drm, !crtc_state->bigjoiner_linked_crtc);
}
/* FIXME: add more state readout as needed */

1
drivers/gpu/drm/i915/display/intel_vdsc.h
View File

@ -22,5 +22,6 @@ void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state);
void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
enum intel_display_power_domain
intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
struct intel_crtc *intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc);
#endif /* __INTEL_VDSC_H__ */

7
drivers/gpu/drm/i915/gem/i915_gem_mman.c
View File

@ -61,10 +61,11 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *obj;
unsigned long addr;
/* mmap ioctl is disallowed for all platforms after TGL-LP. This also
* covers all platforms with local memory.
/*
* mmap ioctl is disallowed for all discrete platforms,
* and for all platforms with GRAPHICS_VER > 12.
*/
if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
if (IS_DGFX(i915) || GRAPHICS_VER(i915) > 12)
return -EOPNOTSUPP;
if (args->flags & ~(I915_MMAP_WC))

55
drivers/gpu/drm/i915/gt/selftest_execlists.c
View File

@ -551,6 +551,32 @@ static int live_pin_rewind(void *arg)
return err;
}
static int engine_lock_reset_tasklet(struct intel_engine_cs *engine)
{
tasklet_disable(&engine->execlists.tasklet);
local_bh_disable();
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
&engine->gt->reset.flags)) {
local_bh_enable();
tasklet_enable(&engine->execlists.tasklet);
intel_gt_set_wedged(engine->gt);
return -EBUSY;
}
return 0;
}
static void engine_unlock_reset_tasklet(struct intel_engine_cs *engine)
{
clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
&engine->gt->reset.flags);
local_bh_enable();
tasklet_enable(&engine->execlists.tasklet);
}
static int live_hold_reset(void *arg)
{
struct intel_gt *gt = arg;
@ -598,15 +624,9 @@ static int live_hold_reset(void *arg)
/* We have our request executing, now remove it and reset */
local_bh_disable();
if (test_and_set_bit(I915_RESET_ENGINE + id,
&gt->reset.flags)) {
local_bh_enable();
intel_gt_set_wedged(gt);
err = -EBUSY;
err = engine_lock_reset_tasklet(engine);
if (err)
goto out;
}
tasklet_disable(&engine->execlists.tasklet);
engine->execlists.tasklet.callback(&engine->execlists.tasklet);
GEM_BUG_ON(execlists_active(&engine->execlists) != rq);
@ -618,10 +638,7 @@ static int live_hold_reset(void *arg)
__intel_engine_reset_bh(engine, NULL);
GEM_BUG_ON(rq->fence.error != -EIO);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(I915_RESET_ENGINE + id,
&gt->reset.flags);
local_bh_enable();
engine_unlock_reset_tasklet(engine);
/* Check that we do not resubmit the held request */
if (!i915_request_wait(rq, 0, HZ / 5)) {
@ -4585,15 +4602,9 @@ static int reset_virtual_engine(struct intel_gt *gt,
GEM_BUG_ON(engine == ve->engine);
/* Take ownership of the reset and tasklet */
local_bh_disable();
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
&gt->reset.flags)) {
local_bh_enable();
intel_gt_set_wedged(gt);
err = -EBUSY;
err = engine_lock_reset_tasklet(engine);
if (err)
goto out_heartbeat;
}
tasklet_disable(&engine->execlists.tasklet);
engine->execlists.tasklet.callback(&engine->execlists.tasklet);
GEM_BUG_ON(execlists_active(&engine->execlists) != rq);
@ -4612,9 +4623,7 @@ static int reset_virtual_engine(struct intel_gt *gt,
GEM_BUG_ON(rq->fence.error != -EIO);
/* Release our grasp on the engine, letting CS flow again */
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags);
local_bh_enable();
engine_unlock_reset_tasklet(engine);
/* Check that we do not resubmit the held request */
i915_request_get(rq);