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MIPS: Move GIC to drivers/irqchip/

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Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig
option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7812/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker 2014-09-18 14:47:19 -07:00 committed by Ralf Baechle
parent 8635233ca5
commit 8a19b8f194
8 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/mips/Kconfig
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@ -320,7 +320,7 @@ config MIPS_MALTA
select GENERIC_ISA_DMA select GENERIC_ISA_DMA
select HAVE_PCSPKR_PLATFORM select HAVE_PCSPKR_PLATFORM
select IRQ_CPU select IRQ_CPU
select IRQ_GIC select MIPS_GIC
select HW_HAS_PCI select HW_HAS_PCI
select I8253 select I8253
select I8259 select I8259
@ -362,7 +362,7 @@ config MIPS_SEAD3
select CPU_MIPSR2_IRQ_EI select CPU_MIPSR2_IRQ_EI
select DMA_NONCOHERENT select DMA_NONCOHERENT
select IRQ_CPU select IRQ_CPU
select IRQ_GIC select MIPS_GIC
select LIBFDT select LIBFDT
select MIPS_MSC select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
@ -1073,10 +1073,6 @@ config IRQ_TXX9
config IRQ_GT641XX config IRQ_GT641XX
bool bool
config IRQ_GIC
select MIPS_CM
bool
config PCI_GT64XXX_PCI0 config PCI_GT64XXX_PCI0
bool bool
@ -1890,7 +1886,7 @@ config FORCE_MAX_ZONEORDER
config CEVT_GIC config CEVT_GIC
bool "Use GIC global counter for clock events" bool "Use GIC global counter for clock events"
depends on IRQ_GIC && !MIPS_SEAD3 depends on MIPS_GIC && !MIPS_SEAD3
help help
Use the GIC global counter for the clock events. The R4K clock Use the GIC global counter for the clock events. The R4K clock
event driver is always present, so if the platform ends up not event driver is always present, so if the platform ends up not

1
arch/mips/kernel/Makefile
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@ -68,7 +68,6 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
obj-$(CONFIG_MIPS_MSC) += irq-msc01.o obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
obj-$(CONFIG_IRQ_GIC) += irq-gic.o
obj-$(CONFIG_KPROBES) += kprobes.o obj-$(CONFIG_KPROBES) += kprobes.o
obj-$(CONFIG_32BIT) += scall32-o32.o obj-$(CONFIG_32BIT) += scall32-o32.o

2
arch/mips/kernel/cevt-r4k.c
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@ -85,7 +85,7 @@ void mips_event_handler(struct clock_event_device *dev)
*/ */
static int c0_compare_int_pending(void) static int c0_compare_int_pending(void)
{ {
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (cpu_has_veic) if (cpu_has_veic)
return gic_get_timer_pending(); return gic_get_timer_pending();
#endif #endif

4
arch/mips/kernel/smp-mt.c
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@ -119,7 +119,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action)
unsigned long flags; unsigned long flags;
int vpflags; int vpflags;
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (gic_present) { if (gic_present) {
gic_send_ipi_single(cpu, action); gic_send_ipi_single(cpu, action);
return; return;
@ -158,7 +158,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
static void vsmp_init_secondary(void) static void vsmp_init_secondary(void)
{ {
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
/* This is Malta specific: IPI,performance and timer interrupts */ /* This is Malta specific: IPI,performance and timer interrupts */
if (gic_present) if (gic_present)
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |

10
arch/mips/mti-malta/malta-time.c
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@ -70,7 +70,7 @@ static void __init estimate_frequencies(void)
{ {
unsigned long flags; unsigned long flags;
unsigned int count, start; unsigned int count, start;
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
unsigned int giccount = 0, gicstart = 0; unsigned int giccount = 0, gicstart = 0;
#endif #endif
@ -87,7 +87,7 @@ static void __init estimate_frequencies(void)
/* Initialize counters. */ /* Initialize counters. */
start = read_c0_count(); start = read_c0_count();
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (gic_present) if (gic_present)
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart); GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
#endif #endif
@ -97,7 +97,7 @@ static void __init estimate_frequencies(void)
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count(); count = read_c0_count();
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (gic_present) if (gic_present)
GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount); GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
#endif #endif
@ -107,7 +107,7 @@ static void __init estimate_frequencies(void)
count -= start; count -= start;
mips_hpt_frequency = count; mips_hpt_frequency = count;
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (gic_present) { if (gic_present) {
giccount -= gicstart; giccount -= gicstart;
gic_frequency = giccount; gic_frequency = giccount;
@ -189,7 +189,7 @@ void __init plat_time_init(void)
setup_pit_timer(); setup_pit_timer();
#endif #endif
#ifdef CONFIG_IRQ_GIC #ifdef CONFIG_MIPS_GIC
if (gic_present) { if (gic_present) {
freq = freqround(gic_frequency, 5000); freq = freqround(gic_frequency, 5000);
printk("GIC frequency %d.%02d MHz\n", freq/1000000, printk("GIC frequency %d.%02d MHz\n", freq/1000000,

4
drivers/irqchip/Kconfig
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@ -125,3 +125,7 @@ config KEYSTONE_IRQ
help help
Support for Texas Instruments Keystone 2 IRQ controller IP which Support for Texas Instruments Keystone 2 IRQ controller IP which
is part of the Keystone 2 IPC mechanism is part of the Keystone 2 IPC mechanism
config MIPS_GIC
bool
select MIPS_CM

1
drivers/irqchip/Makefile
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@ -38,3 +38,4 @@ obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \ obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
irq-bcm7120-l2.o irq-bcm7120-l2.o
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o

0
arch/mips/kernel/irq-gic.c → drivers/irqchip/irq-mips-gic.c
View File