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This pull request contains Broadcom ARM64-based SoCs Device Tree changes for

Browse Source 
4.13. Please note the following from Eric:
 
 I've based this summary on the bcm2835-dt-next tag, to clarify what's in this
 patch series, but it does require being careful since it involves a cross-merge
 between branches.
 
 - Anup documents the Broadcom Stingray binding, common clocks, adds initial
   support for the Stingray DTSI and DTS files and adds support for the PL022,
   PL330 and SP805
 
 - Sandeep adds the clock nodes to the Stingray Device Tree nodes
 
 - Pramod adds support for the NAND, pinctrl, GPIO to the Stingray Device Tree nodes
 
 - Oza adds I2C Device Tree nodes to the Stingray DTSes
 
 - Srinath adds PWM and SDHCI Device Tree nodes for the Stingray SoC
 
 - Ravijeta adds support for the USB Dual Role PHY on Northstar 2
 
 - Gerd starts adding references to the sdhost and sdhci controllers, and then
   switches the sdcard to to use the SDHOST (faster than SDHCI)
 
 - Stefan defines the BCM2837 thermal coefficients in order for the Raspberry Pi
   thermal driver to work correctly
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Merge tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

This pull request contains Broadcom ARM64-based SoCs Device Tree changes for
4.13. Please note the following from Eric:

I've based this summary on the bcm2835-dt-next tag, to clarify what's in this
patch series, but it does require being careful since it involves a cross-merge
between branches.

- Anup documents the Broadcom Stingray binding, common clocks, adds initial
  support for the Stingray DTSI and DTS files and adds support for the PL022,
  PL330 and SP805

- Sandeep adds the clock nodes to the Stingray Device Tree nodes

- Pramod adds support for the NAND, pinctrl, GPIO to the Stingray Device Tree nodes

- Oza adds I2C Device Tree nodes to the Stingray DTSes

- Srinath adds PWM and SDHCI Device Tree nodes for the Stingray SoC

- Ravijeta adds support for the USB Dual Role PHY on Northstar 2

- Gerd starts adding references to the sdhost and sdhci controllers, and then
  switches the sdcard to to use the SDHOST (faster than SDHCI)

- Stefan defines the BCM2837 thermal coefficients in order for the Raspberry Pi
  thermal driver to work correctly

* tag 'arm-soc/for-4.13/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: Add USB DRD PHY device tree node
  ARM64: dts: bcm2837: Define CPU thermal coefficients
  arm64: dts: Add PWM and SDHCI DT nodes for Stingray SOC
  arm64: dts: Add PL022, PL330 and SP805 DT nodes for Stingray
  arm64: dts: Add I2C DT nodes for Stingray SoC
  arm64: dts: Add GPIO DT nodes for Stingray SOC
  arm64: dts: Add pinctrl DT nodes for Stingray SOC
  arm64: dts: Add NAND DT nodes for Stingray SOC
  arm64: dts: Add clock DT nodes for Stingray SOC
  arm64: dts: Initial DTS files for Broadcom Stingray SOC
  dt-bindings: clk: Extend binding doc for Stingray SOC
  dt-bindings: bcm: Add Broadcom Stingray bindings document
  ARM: dts: bcm283x: switch from &sdhci to &sdhost
  arm64: dts: bcm2837: add &sdhci and &sdhost
  ARM: dts: bcm283x: Add CPU thermal zone with 1 trip point
  ARM: dts: Add devicetree for the Raspberry Pi 3, for arm32 (v6)

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-06-18 20:18:44 -07:00
commit 8aba614385
21 changed files with 1555 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
Documentation/devicetree/bindings/arm/bcm/brcm,stingray.txt Normal file
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@ -0,0 +1,12 @@
Broadcom Stingray device tree bindings
------------------------------------------------
Boards with Stingray shall have the following properties:
Required root node property:
Stingray Combo SVK board
compatible = "brcm,bcm958742k", "brcm,stingray";
Stingray SST100 board
compatible = "brcm,bcm958742t", "brcm,stingray";

76
Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt
View File

@ -219,3 +219,79 @@ BCM63138
--------
PLL and leaf clock compatible strings for BCM63138 are:
"brcm,bcm63138-armpll"
Stingray
-----------
PLL and leaf clock compatible strings for Stingray are:
"brcm,sr-genpll0"
"brcm,sr-genpll1"
"brcm,sr-genpll2"
"brcm,sr-genpll3"
"brcm,sr-genpll4"
"brcm,sr-genpll5"
"brcm,sr-genpll6"
"brcm,sr-lcpll0"
"brcm,sr-lcpll1"
"brcm,sr-lcpll-pcie"
The following table defines the set of PLL/clock index and ID for Stingray.
These clock IDs are defined in:
"include/dt-bindings/clock/bcm-sr.h"
Clock Source Index ID
--- ----- ----- ---------
crystal N/A N/A N/A
crmu_ref25m crystal N/A N/A
genpll0 crystal 0 BCM_SR_GENPLL0
clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
genpll1 crystal 0 BCM_SR_GENPLL1
clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
genpll2 crystal 0 BCM_SR_GENPLL2
clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH
genpll3 crystal 0 BCM_SR_GENPLL3
clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
genpll4 crystal 0 BCM_SR_GENPLL4
ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK
clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
genpll5 crystal 0 BCM_SR_GENPLL5
fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
genpll6 crystal 0 BCM_SR_GENPLL6
48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
lcpll0 crystal 0 BCM_SR_LCPLL0
clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK
sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK
lcpll1 crystal 0 BCM_SR_LCPLL1
wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK
lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK

1
arch/arm/boot/dts/Makefile
View File

@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-a-plus.dtb \
bcm2836-rpi-2-b.dtb \
bcm2837-rpi-3-b.dtb \
bcm2835-rpi-zero.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \

2
arch/arm/boot/dts/bcm2835-rpi.dtsi
View File

@ -65,13 +65,13 @@
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio48>;
status = "okay";
bus-width = <4>;
};
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};

4
arch/arm/boot/dts/bcm2835.dtsi
View File

@ -24,6 +24,10 @@
};
};
&cpu_thermal {
coefficients = <(-538) 407000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2835-thermal";

4
arch/arm/boot/dts/bcm2836.dtsi
View File

@ -77,6 +77,10 @@
interrupts = <8>;
};
&cpu_thermal {
coefficients = <(-538) 407000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2836-thermal";

1
arch/arm/boot/dts/bcm2837-rpi-3-b.dts Normal file
View File

@ -0,0 +1 @@
#include "arm64/broadcom/bcm2837-rpi-3-b.dts"

21
arch/arm/boot/dts/bcm283x.dtsi
View File

@ -19,6 +19,26 @@
bootargs = "earlyprintk console=ttyAMA0";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <80000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -430,6 +450,7 @@
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
#thermal-sensor-cells = <0>;
status = "disabled";
};

1
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
dts-dirs := stingray
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

17
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
View File

@ -22,3 +22,20 @@
&uart1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
pinctrl-0 = <&sdhost_gpio48>;
status = "okay";
bus-width = <4>;
};

4
arch/arm64/boot/dts/broadcom/bcm2837.dtsi
View File

@ -75,6 +75,10 @@
interrupts = <8>;
};
&cpu_thermal {
coefficients = <(-538) 412000>;
};
/* enable thermal sensor with the correct compatible property set */
&thermal {
compatible = "brcm,bcm2837-thermal";

14
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -460,6 +460,20 @@
};
};
usbdrd_phy: phy@66000960 {
#phy-cells = <0>;
compatible = "brcm,ns2-drd-phy";
reg = <0x66000960 0x24>,
<0x67012800 0x4>,
<0x6501d148 0x4>,
<0x664d0700 0x4>;
reg-names = "icfg", "rst-ctrl",
"crmu-ctrl", "usb2-strap";
id-gpios = <&gpio_g 30 0>;
vbus-gpios = <&gpio_g 31 0>;
status = "disabled";
};
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;

6
arch/arm64/boot/dts/broadcom/stingray/Makefile Normal file
View File

@ -0,0 +1,6 @@
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

131
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi Normal file
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@ -0,0 +1,131 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stingray.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart1;
serial1 = &uart0;
serial2 = &uart2;
serial3 = &uart3;
};
sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio0_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 18 0>;
states = <3300000 0x0
1800000 0x1>;
};
sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl {
compatible = "regulator-gpio";
regulator-name = "sdio1_vddo_ctrl_reg";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&pca9505 19 0>;
states = <3300000 0x0
1800000 0x1>;
};
};
&memory { /* Default DRAM banks */
reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
&uart1 {
status = "okay";
};
&pwm {
status = "okay";
};
&i2c0 {
status = "okay";
pca9505: pca9505@20 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
};
&i2c1 {
status = "okay";
pcf8574: pcf8574@20 {
compatible = "nxp,pcf8574a";
gpio-controller;
#gpio-cells = <2>;
reg = <0x27>;
};
};
&nand {
status = "ok";
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&sdio0 {
vqmmc-supply = <&sdio0_vddo_ctrl_reg>;
non-removable;
full-pwr-cycle;
status = "okay";
};
&sdio1 {
vqmmc-supply = <&sdio1_vddo_ctrl_reg>;
full-pwr-cycle;
status = "okay";
};

78
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts Normal file
View File

@ -0,0 +1,78 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742k", "brcm,stingray";
model = "Stingray Combo SVK (BCM958742K)";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&ssp0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 34 0>;
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&ssp1 {
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio_hsls 96 0>;
status = "okay";
spi-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

40
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts Normal file
View File

@ -0,0 +1,40 @@
/*
* BSD LICENSE
*
* Copyright(c) 2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm958742-base.dtsi"
/ {
compatible = "brcm,bcm958742t", "brcm,stingray";
model = "Stingray SST100 (BCM958742T)";
};

170
arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi Normal file
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@ -0,0 +1,170 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-sr.h>
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
crmu_ref25m: crmu_ref25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&osc>;
clock-div = <2>;
clock-mult = <1>;
};
genpll0: genpll0@0001d104 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll0";
reg = <0x0001d104 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll0", "clk_125", "clk_scr",
"clk_250", "clk_pcie_axi",
"clk_paxc_axi_x2",
"clk_paxc_axi";
};
genpll3: genpll3@0001d1e0 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll3";
reg = <0x0001d1e0 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll3", "clk_hsls",
"clk_sdio";
};
genpll4: genpll4@0001d214 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll4";
reg = <0x0001d214 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll4", "clk_ccn",
"clk_tpiu_pll", "noc_clk",
"pll_chclk_fs4",
"clk_bridge_fscpu";
};
genpll5: genpll5@0001d248 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll5";
reg = <0x0001d248 0x32>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "genpll5", "fs4_hf_clk",
"crypto_ae_clk", "raid_ae_clk";
};
lcpll0: lcpll0@0001d0c4 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll0";
reg = <0x0001d0c4 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll0", "clk_sata_refp",
"clk_sata_refn", "clk_sata_350",
"clk_sata_500";
};
lcpll1: lcpll1@0001d138 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll1";
reg = <0x0001d138 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll1", "clk_wanpn",
"clk_usb_ref",
"timesync_evt_clk";
};
hsls_clk: hsls_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 1>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_div2_clk: hsls_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
hsls_div4_clk: hsls_div4_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
hsls_25m_clk: hsls_25m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&crmu_ref25m>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_25m_div2_clk: hsls_25m_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hsls_25m_clk>;
clock-div = <2>;
clock-mult = <1>;
};
sdio0_clk: sdio0_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};
sdio1_clk: sdio1_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};

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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
pinconf: pinconf@00140000 {
compatible = "pinconf-single";
reg = <0x00140000 0x250>;
pinctrl-single,register-width = <32>;
/* pinconf functions */
};
pinmux: pinmux@0014029c {
compatible = "pinctrl-single";
reg = <0x0014029c 0x250>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = <
&range 0 154 MODE_GPIO
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
/* pinctrl functions */
tsio_pins: pinmux_gpio_14 {
pinctrl-single,pins = <
0x038 MODE_NITRO /* tsio_0 */
0x03c MODE_NITRO /* tsio_1 */
>;
};
nor_pins: pinmux_pnor_adv_n {
pinctrl-single,pins = <
0x0ac MODE_PNOR /* nand_ce1_n */
0x0b0 MODE_PNOR /* nand_ce0_n */
0x0b4 MODE_PNOR /* nand_we_n */
0x0b8 MODE_PNOR /* nand_wp_n */
0x0bc MODE_PNOR /* nand_re_n */
0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
0x0c4 MODE_PNOR /* nand_io0_0 */
0x0c8 MODE_PNOR /* nand_io1_0 */
0x0cc MODE_PNOR /* nand_io2_0 */
0x0d0 MODE_PNOR /* nand_io3_0 */
0x0d4 MODE_PNOR /* nand_io4_0 */
0x0d8 MODE_PNOR /* nand_io5_0 */
0x0dc MODE_PNOR /* nand_io6_0 */
0x0e0 MODE_PNOR /* nand_io7_0 */
0x0e4 MODE_PNOR /* nand_io8_0 */
0x0e8 MODE_PNOR /* nand_io9_0 */
0x0ec MODE_PNOR /* nand_io10_0 */
0x0f0 MODE_PNOR /* nand_io11_0 */
0x0f4 MODE_PNOR /* nand_io12_0 */
0x0f8 MODE_PNOR /* nand_io13_0 */
0x0fc MODE_PNOR /* nand_io14_0 */
0x100 MODE_PNOR /* nand_io15_0 */
0x104 MODE_PNOR /* nand_ale_0 */
0x108 MODE_PNOR /* nand_cle_0 */
0x040 MODE_PNOR /* pnor_adv_n */
0x044 MODE_PNOR /* pnor_baa_n */
0x048 MODE_PNOR /* pnor_bls_0_n */
0x04c MODE_PNOR /* pnor_bls_1_n */
0x050 MODE_PNOR /* pnor_cre */
0x054 MODE_PNOR /* pnor_cs_2_n */
0x058 MODE_PNOR /* pnor_cs_1_n */
0x05c MODE_PNOR /* pnor_cs_0_n */
0x060 MODE_PNOR /* pnor_we_n */
0x064 MODE_PNOR /* pnor_oe_n */
0x068 MODE_PNOR /* pnor_intr */
0x06c MODE_PNOR /* pnor_dat_0 */
0x070 MODE_PNOR /* pnor_dat_1 */
0x074 MODE_PNOR /* pnor_dat_2 */
0x078 MODE_PNOR /* pnor_dat_3 */
0x07c MODE_PNOR /* pnor_dat_4 */
0x080 MODE_PNOR /* pnor_dat_5 */
0x084 MODE_PNOR /* pnor_dat_6 */
0x088 MODE_PNOR /* pnor_dat_7 */
0x08c MODE_PNOR /* pnor_dat_8 */
0x090 MODE_PNOR /* pnor_dat_9 */
0x094 MODE_PNOR /* pnor_dat_10 */
0x098 MODE_PNOR /* pnor_dat_11 */
0x09c MODE_PNOR /* pnor_dat_12 */
0x0a0 MODE_PNOR /* pnor_dat_13 */
0x0a4 MODE_PNOR /* pnor_dat_14 */
0x0a8 MODE_PNOR /* pnor_dat_15 */
>;
};
nand_pins: pinmux_nand_ce1_n {
pinctrl-single,pins = <
0x0ac MODE_NAND /* nand_ce1_n */
0x0b0 MODE_NAND /* nand_ce0_n */
0x0b4 MODE_NAND /* nand_we_n */
0x0b8 MODE_NAND /* nand_wp_n */
0x0bc MODE_NAND /* nand_re_n */
0x0c0 MODE_NAND /* nand_rdy_bsy_n */
0x0c4 MODE_NAND /* nand_io0_0 */
0x0c8 MODE_NAND /* nand_io1_0 */
0x0cc MODE_NAND /* nand_io2_0 */
0x0d0 MODE_NAND /* nand_io3_0 */
0x0d4 MODE_NAND /* nand_io4_0 */
0x0d8 MODE_NAND /* nand_io5_0 */
0x0dc MODE_NAND /* nand_io6_0 */
0x0e0 MODE_NAND /* nand_io7_0 */
0x0e4 MODE_NAND /* nand_io8_0 */
0x0e8 MODE_NAND /* nand_io9_0 */
0x0ec MODE_NAND /* nand_io10_0 */
0x0f0 MODE_NAND /* nand_io11_0 */
0x0f4 MODE_NAND /* nand_io12_0 */
0x0f8 MODE_NAND /* nand_io13_0 */
0x0fc MODE_NAND /* nand_io14_0 */
0x100 MODE_NAND /* nand_io15_0 */
0x104 MODE_NAND /* nand_ale_0 */
0x108 MODE_NAND /* nand_cle_0 */
>;
};
pwm0_pins: pinmux_pwm_0 {
pinctrl-single,pins = <
0x10c MODE_NITRO
>;
};
pwm1_pins: pinmux_pwm_1 {
pinctrl-single,pins = <
0x110 MODE_NITRO
>;
};
pwm2_pins: pinmux_pwm_2 {
pinctrl-single,pins = <
0x114 MODE_NITRO
>;
};
pwm3_pins: pinmux_pwm_3 {
pinctrl-single,pins = <
0x118 MODE_NITRO
>;
};
dbu_rxd_pins: pinmux_uart1_sin_nitro {
pinctrl-single,pins = <
0x11c MODE_NITRO /* dbu_rxd */
0x120 MODE_NITRO /* dbu_txd */
>;
};
uart1_pins: pinmux_uart1_sin_nand {
pinctrl-single,pins = <
0x11c MODE_NAND /* uart1_sin */
0x120 MODE_NAND /* uart1_out */
>;
};
uart2_pins: pinmux_uart2_sin {
pinctrl-single,pins = <
0x124 MODE_NITRO /* uart2_sin */
0x128 MODE_NITRO /* uart2_out */
>;
};
uart3_pins: pinmux_uart3_sin {
pinctrl-single,pins = <
0x12c MODE_NITRO /* uart3_sin */
0x130 MODE_NITRO /* uart3_out */
>;
};
i2s_pins: pinmux_i2s_bitclk {
pinctrl-single,pins = <
0x134 MODE_NITRO /* i2s_bitclk */
0x138 MODE_NITRO /* i2s_sdout */
0x13c MODE_NITRO /* i2s_sdin */
0x140 MODE_NITRO /* i2s_ws */
0x144 MODE_NITRO /* i2s_mclk */
0x148 MODE_NITRO /* i2s_spdif_out */
>;
};
qspi_pins: pinumx_qspi_hold_n {
pinctrl-single,pins = <
0x14c MODE_NAND /* qspi_hold_n */
0x150 MODE_NAND /* qspi_wp_n */
0x154 MODE_NAND /* qspi_sck */
0x158 MODE_NAND /* qspi_cs_n */
0x15c MODE_NAND /* qspi_mosi */
0x160 MODE_NAND /* qspi_miso */
>;
};
mdio_pins: pinumx_ext_mdio {
pinctrl-single,pins = <
0x164 MODE_NITRO /* ext_mdio */
0x168 MODE_NITRO /* ext_mdc */
>;
};
i2c0_pins: pinmux_i2c0_sda {
pinctrl-single,pins = <
0x16c MODE_NITRO /* i2c0_sda */
0x170 MODE_NITRO /* i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1_sda {
pinctrl-single,pins = <
0x174 MODE_NITRO /* i2c1_sda */
0x178 MODE_NITRO /* i2c1_scl */
>;
};
sdio0_pins: pinmux_sdio0_cd_l {
pinctrl-single,pins = <
0x17c MODE_NITRO /* sdio0_cd_l */
0x180 MODE_NITRO /* sdio0_clk_sdcard */
0x184 MODE_NITRO /* sdio0_data0 */
0x188 MODE_NITRO /* sdio0_data1 */
0x18c MODE_NITRO /* sdio0_data2 */
0x190 MODE_NITRO /* sdio0_data3 */
0x194 MODE_NITRO /* sdio0_data4 */
0x198 MODE_NITRO /* sdio0_data5 */
0x19c MODE_NITRO /* sdio0_data6 */
0x1a0 MODE_NITRO /* sdio0_data7 */
0x1a4 MODE_NITRO /* sdio0_cmd */
0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
0x1ac MODE_NITRO /* sdio0_led_on */
0x1b0 MODE_NITRO /* sdio0_wp */
>;
};
sdio1_pins: pinmux_sdio1_cd_l {
pinctrl-single,pins = <
0x1b4 MODE_NITRO /* sdio1_cd_l */
0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
0x1bc MODE_NITRO /* sdio1_data0 */
0x1c0 MODE_NITRO /* sdio1_data1 */
0x1c4 MODE_NITRO /* sdio1_data2 */
0x1c8 MODE_NITRO /* sdio1_data3 */
0x1cc MODE_NITRO /* sdio1_data4 */
0x1d0 MODE_NITRO /* sdio1_data5 */
0x1d4 MODE_NITRO /* sdio1_data6 */
0x1d8 MODE_NITRO /* sdio1_data7 */
0x1dc MODE_NITRO /* sdio1_cmd */
0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
0x1e4 MODE_NITRO /* sdio1_led_on */
0x1e8 MODE_NITRO /* sdio1_wp */
>;
};
spi0_pins: pinmux_spi0_sck_nand {
pinctrl-single,pins = <
0x1ec MODE_NITRO /* spi0_sck */
0x1f0 MODE_NITRO /* spi0_rxd */
0x1f4 MODE_NITRO /* spi0_fss */
0x1f8 MODE_NITRO /* spi0_txd */
>;
};
spi1_pins: pinmux_spi1_sck_nand {
pinctrl-single,pins = <
0x1fc MODE_NITRO /* spi1_sck */
0x200 MODE_NITRO /* spi1_rxd */
0x204 MODE_NITRO /* spi1_fss */
0x208 MODE_NITRO /* spi1_txd */
>;
};
nuart_pins: pinmux_uart0_sin_nitro {
pinctrl-single,pins = <
0x20c MODE_NITRO /* nuart_rxd */
0x210 MODE_NITRO /* nuart_txd */
>;
};
uart0_pins: pinumux_uart0_sin_nand {
pinctrl-single,pins = <
0x20c MODE_NAND /* uart0_sin */
0x210 MODE_NAND /* uart0_out */
0x214 MODE_NAND /* uart0_rts */
0x218 MODE_NAND /* uart0_cts */
0x21c MODE_NAND /* uart0_dtr */
0x220 MODE_NAND /* uart0_dcd */
0x224 MODE_NAND /* uart0_dsr */
0x228 MODE_NAND /* uart0_ri */
>;
};
drdu2_pins: pinmux_drdu2_overcurrent {
pinctrl-single,pins = <
0x22c MODE_NITRO /* drdu2_overcurrent */
0x230 MODE_NITRO /* drdu2_vbus_ppc */
0x234 MODE_NITRO /* drdu2_vbus_present */
0x238 MODE_NITRO /* drdu2_id */
>;
};
drdu3_pins: pinmux_drdu3_overcurrent {
pinctrl-single,pins = <
0x23c MODE_NITRO /* drdu3_overcurrent */
0x240 MODE_NITRO /* drdu3_vbus_ppc */
0x244 MODE_NITRO /* drdu3_vbus_present */
0x248 MODE_NITRO /* drdu3_id */
>;
};
usb3h_pins: pinmux_usb3h_overcurrent {
pinctrl-single,pins = <
0x24c MODE_NITRO /* usb3h_overcurrent */
0x250 MODE_NITRO /* usb3h_vbus_ppc */
>;
};
};

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/*
* BSD LICENSE
*
* Copyright(c) 2015-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,stingray";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@001 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x201>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x0 0x301>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
};
CLUSTER0_L2: l2-cache@000 {
compatible = "cache";
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
};
};
memory: memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
scr {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
gic: interrupt-controller@02c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
reg = <0x02c00000 0x010000>, /* GICD */
<0x02e00000 0x600000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@63c20000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x02c20000 0x10000>;
};
};
smmu: mmu@03000000 {
compatible = "arm,mmu-500";
reg = <0x03000000 0x80000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <2>;
};
};
crmu: crmu {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x66400000 0x100000>;
#include "stingray-clock.dtsi"
gpio_crmu: gpio@00024800 {
compatible = "brcm,iproc-gpio";
reg = <0x00024800 0x4c>;
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
};
};
hsls {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x68900000 0x17700000>;
#include "stingray-pinctrl.dtsi"
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
clocks = <&crmu_ref25m>;
#pwm-cells = <3>;
status = "disabled";
};
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
wdt0: watchdog@000c0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x000c0000 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdogclk", "apb_pclk";
};
gpio_hsls: gpio@000d0000 {
compatible = "brcm,iproc-gpio";
reg = <0x000d0000 0x864>;
ngpios = <151>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinmux 0 0 16>,
<&pinmux 16 71 2>,
<&pinmux 18 131 8>,
<&pinmux 26 83 6>,
<&pinmux 32 123 4>,
<&pinmux 36 43 24>,
<&pinmux 60 89 2>,
<&pinmux 62 73 4>,
<&pinmux 66 95 28>,
<&pinmux 94 127 4>,
<&pinmux 98 139 10>,
<&pinmux 108 16 27>,
<&pinmux 135 77 6>,
<&pinmux 141 67 4>,
<&pinmux 145 149 6>,
<&pinmux 151 91 4>;
};
i2c1: i2c@000e0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000e0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: uart@00100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart1: uart@00110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: uart@00120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: uart@00130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
ssp0: ssp@00180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00180000 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "spiclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssp1: ssp@00190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00190000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
clock-names = "spiclk", "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hwrng: hwrng@00220000 {
compatible = "brcm,iproc-rng200";
reg = <0x00220000 0x28>;
};
dma0: dma@00310000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x00310000 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&hsls_div2_clk>;
clock-names = "apb_pclk";
iommus = <&smmu 0x6000 0x0000>;
};
nand: nand@00360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,
<0x0050a408 0x600>,
<0x00360f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
status = "disabled";
};
sdio0: sdhci@003f1000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f1000 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio0_clk>;
iommus = <&smmu 0x6002 0x0000>;
status = "disabled";
};
sdio1: sdhci@003f2000 {
compatible = "brcm,sdhci-iproc";
reg = <0x003f2000 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&sdio1_clk>;
iommus = <&smmu 0x6003 0x0000>;
status = "disabled";
};
};
};

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/*
* BSD LICENSE
*
* Copyright(c) 2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_BCM_SR_H
#define _CLOCK_BCM_SR_H
/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
#define BCM_SR_GENPLL0 0
#define BCM_SR_GENPLL0_SATA_CLK 1
#define BCM_SR_GENPLL0_SCR_CLK 2
#define BCM_SR_GENPLL0_250M_CLK 3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
/* GENPLL 1 clock channel ID MHB PCIE NITRO */
#define BCM_SR_GENPLL1 0
#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
#define BCM_SR_GENPLL1_MHB_APB_CLK 2
/* GENPLL 2 clock channel ID NITRO MHB*/
#define BCM_SR_GENPLL2 0
#define BCM_SR_GENPLL2_NIC_CLK 1
#define BCM_SR_GENPLL2_250_NITRO_CLK 2
#define BCM_SR_GENPLL2_125_NITRO_CLK 3
#define BCM_SR_GENPLL2_CHIMP_CLK 4
/* GENPLL 3 HSLS clock channel ID */
#define BCM_SR_GENPLL3 0
#define BCM_SR_GENPLL3_HSLS_CLK 1
#define BCM_SR_GENPLL3_SDIO_CLK 2
/* GENPLL 4 SCR clock channel ID */
#define BCM_SR_GENPLL4 0
#define BCM_SR_GENPLL4_CCN_CLK 1
/* GENPLL 5 FS4 clock channel ID */
#define BCM_SR_GENPLL5 0
#define BCM_SR_GENPLL5_FS_CLK 1
#define BCM_SR_GENPLL5_SPU_CLK 2
/* GENPLL 6 NITRO clock channel ID */
#define BCM_SR_GENPLL6 0
#define BCM_SR_GENPLL6_48_USB_CLK 1
/* LCPLL0 clock channel ID */
#define BCM_SR_LCPLL0 0
#define BCM_SR_LCPLL0_SATA_REF_CLK 1
#define BCM_SR_LCPLL0_USB_REF_CLK 2
#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
/* LCPLL1 clock channel ID */
#define BCM_SR_LCPLL1 0
#define BCM_SR_LCPLL1_WAN_CLK 1
/* LCPLL PCIE clock channel ID */
#define BCM_SR_LCPLL_PCIE 0
#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
/* GENPLL EMEM0 clock channel ID */
#define BCM_SR_EMEMPLL0 0
#define BCM_SR_EMEMPLL0_EMEM_CLK 1
/* GENPLL EMEM0 clock channel ID */
#define BCM_SR_EMEMPLL1 0
#define BCM_SR_EMEMPLL1_EMEM_CLK 1
/* GENPLL EMEM0 clock channel ID */
#define BCM_SR_EMEMPLL2 0
#define BCM_SR_EMEMPLL2_EMEM_CLK 1
#endif /* _CLOCK_BCM_SR_H */

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include/dt-bindings/pinctrl/brcm,pinctrl-stingray.h Normal file
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/*
* BSD LICENSE
*
* Copyright(c) 2017 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__
/* Alternate functions available in MUX controller */
#define MODE_NITRO 0
#define MODE_NAND 1
#define MODE_PNOR 2
#define MODE_GPIO 3
/* Pad configuration attribute */
#define PAD_SLEW_RATE_ENA (1 << 0)
#define PAD_SLEW_RATE_ENA_MASK (1 << 0)
#define PAD_DRIVE_STRENGTH_2_MA (0 << 1)
#define PAD_DRIVE_STRENGTH_4_MA (1 << 1)
#define PAD_DRIVE_STRENGTH_6_MA (2 << 1)
#define PAD_DRIVE_STRENGTH_8_MA (3 << 1)
#define PAD_DRIVE_STRENGTH_10_MA (4 << 1)
#define PAD_DRIVE_STRENGTH_12_MA (5 << 1)
#define PAD_DRIVE_STRENGTH_14_MA (6 << 1)
#define PAD_DRIVE_STRENGTH_16_MA (7 << 1)
#define PAD_DRIVE_STRENGTH_MASK (7 << 1)
#define PAD_PULL_UP_ENA (1 << 4)
#define PAD_PULL_UP_ENA_MASK (1 << 4)
#define PAD_PULL_DOWN_ENA (1 << 5)
#define PAD_PULL_DOWN_ENA_MASK (1 << 5)
#define PAD_INPUT_PATH_DIS (1 << 6)
#define PAD_INPUT_PATH_DIS_MASK (1 << 6)
#define PAD_HYSTERESIS_ENA (1 << 7)
#define PAD_HYSTERESIS_ENA_MASK (1 << 7)
#endif