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KVM: selftests: Rename 'msr->available' to 'msr->fault_exepected' in hyperv_features test

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It may not be clear what 'msr->available' means. The test actually
checks that accessing the particular MSR doesn't cause #GP, rename
the variable accordingly.

While on it, use 'true'/'false' instead of '1'/'0' for 'write'/
'fault_expected' as these are boolean.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20221013095849.705943-5-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Vitaly Kuznetsov 2022-10-13 11:58:46 +02:00 committed by Paolo Bonzini
parent 4e5bf89f27
commit 8b0a62fd38
1 changed files with 92 additions and 92 deletions
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184
tools/testing/selftests/kvm/x86_64/hyperv_features.c
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@ -15,7 +15,7 @@
struct msr_data { struct msr_data {
uint32_t idx; uint32_t idx;
bool available; bool fault_expected;
bool write; bool write;
u64 write_val; u64 write_val;
}; };
@ -38,10 +38,10 @@ static void guest_msr(struct msr_data *msr)
else else
vector = wrmsr_safe(msr->idx, msr->write_val); vector = wrmsr_safe(msr->idx, msr->write_val);
if (msr->available) if (msr->fault_expected)
GUEST_ASSERT_2(!vector, msr->idx, vector);
else
GUEST_ASSERT_2(vector == GP_VECTOR, msr->idx, vector); GUEST_ASSERT_2(vector == GP_VECTOR, msr->idx, vector);
else
GUEST_ASSERT_2(!vector, msr->idx, vector);
GUEST_DONE(); GUEST_DONE();
} }
@ -134,13 +134,13 @@ static void guest_test_msrs_access(void)
* Only available when Hyper-V identification is set * Only available when Hyper-V identification is set
*/ */
msr->idx = HV_X64_MSR_GUEST_OS_ID; msr->idx = HV_X64_MSR_GUEST_OS_ID;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 1: case 1:
msr->idx = HV_X64_MSR_HYPERCALL; msr->idx = HV_X64_MSR_HYPERCALL;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 2: case 2:
feat->eax |= HV_MSR_HYPERCALL_AVAILABLE; feat->eax |= HV_MSR_HYPERCALL_AVAILABLE;
@ -149,118 +149,118 @@ static void guest_test_msrs_access(void)
* HV_X64_MSR_HYPERCALL available. * HV_X64_MSR_HYPERCALL available.
*/ */
msr->idx = HV_X64_MSR_GUEST_OS_ID; msr->idx = HV_X64_MSR_GUEST_OS_ID;
msr->write = 1; msr->write = true;
msr->write_val = HYPERV_LINUX_OS_ID; msr->write_val = HYPERV_LINUX_OS_ID;
msr->available = 1; msr->fault_expected = false;
break; break;
case 3: case 3:
msr->idx = HV_X64_MSR_GUEST_OS_ID; msr->idx = HV_X64_MSR_GUEST_OS_ID;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 4: case 4:
msr->idx = HV_X64_MSR_HYPERCALL; msr->idx = HV_X64_MSR_HYPERCALL;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 5: case 5:
msr->idx = HV_X64_MSR_VP_RUNTIME; msr->idx = HV_X64_MSR_VP_RUNTIME;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 6: case 6:
feat->eax |= HV_MSR_VP_RUNTIME_AVAILABLE; feat->eax |= HV_MSR_VP_RUNTIME_AVAILABLE;
msr->idx = HV_X64_MSR_VP_RUNTIME; msr->idx = HV_X64_MSR_VP_RUNTIME;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 7: case 7:
/* Read only */ /* Read only */
msr->idx = HV_X64_MSR_VP_RUNTIME; msr->idx = HV_X64_MSR_VP_RUNTIME;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 0; msr->fault_expected = true;
break; break;
case 8: case 8:
msr->idx = HV_X64_MSR_TIME_REF_COUNT; msr->idx = HV_X64_MSR_TIME_REF_COUNT;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 9: case 9:
feat->eax |= HV_MSR_TIME_REF_COUNT_AVAILABLE; feat->eax |= HV_MSR_TIME_REF_COUNT_AVAILABLE;
msr->idx = HV_X64_MSR_TIME_REF_COUNT; msr->idx = HV_X64_MSR_TIME_REF_COUNT;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 10: case 10:
/* Read only */ /* Read only */
msr->idx = HV_X64_MSR_TIME_REF_COUNT; msr->idx = HV_X64_MSR_TIME_REF_COUNT;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 0; msr->fault_expected = true;
break; break;
case 11: case 11:
msr->idx = HV_X64_MSR_VP_INDEX; msr->idx = HV_X64_MSR_VP_INDEX;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 12: case 12:
feat->eax |= HV_MSR_VP_INDEX_AVAILABLE; feat->eax |= HV_MSR_VP_INDEX_AVAILABLE;
msr->idx = HV_X64_MSR_VP_INDEX; msr->idx = HV_X64_MSR_VP_INDEX;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 13: case 13:
/* Read only */ /* Read only */
msr->idx = HV_X64_MSR_VP_INDEX; msr->idx = HV_X64_MSR_VP_INDEX;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 0; msr->fault_expected = true;
break; break;
case 14: case 14:
msr->idx = HV_X64_MSR_RESET; msr->idx = HV_X64_MSR_RESET;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 15: case 15:
feat->eax |= HV_MSR_RESET_AVAILABLE; feat->eax |= HV_MSR_RESET_AVAILABLE;
msr->idx = HV_X64_MSR_RESET; msr->idx = HV_X64_MSR_RESET;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 16: case 16:
msr->idx = HV_X64_MSR_RESET; msr->idx = HV_X64_MSR_RESET;
msr->write = 1; msr->write = true;
msr->write_val = 0; msr->write_val = 0;
msr->available = 1; msr->fault_expected = false;
break; break;
case 17: case 17:
msr->idx = HV_X64_MSR_REFERENCE_TSC; msr->idx = HV_X64_MSR_REFERENCE_TSC;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 18: case 18:
feat->eax |= HV_MSR_REFERENCE_TSC_AVAILABLE; feat->eax |= HV_MSR_REFERENCE_TSC_AVAILABLE;
msr->idx = HV_X64_MSR_REFERENCE_TSC; msr->idx = HV_X64_MSR_REFERENCE_TSC;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 19: case 19:
msr->idx = HV_X64_MSR_REFERENCE_TSC; msr->idx = HV_X64_MSR_REFERENCE_TSC;
msr->write = 1; msr->write = true;
msr->write_val = 0; msr->write_val = 0;
msr->available = 1; msr->fault_expected = false;
break; break;
case 20: case 20:
msr->idx = HV_X64_MSR_EOM; msr->idx = HV_X64_MSR_EOM;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 21: case 21:
/* /*
@ -268,146 +268,146 @@ static void guest_test_msrs_access(void)
* capability enabled and guest visible CPUID bit unset. * capability enabled and guest visible CPUID bit unset.
*/ */
msr->idx = HV_X64_MSR_EOM; msr->idx = HV_X64_MSR_EOM;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 22: case 22:
feat->eax |= HV_MSR_SYNIC_AVAILABLE; feat->eax |= HV_MSR_SYNIC_AVAILABLE;
msr->idx = HV_X64_MSR_EOM; msr->idx = HV_X64_MSR_EOM;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 23: case 23:
msr->idx = HV_X64_MSR_EOM; msr->idx = HV_X64_MSR_EOM;
msr->write = 1; msr->write = true;
msr->write_val = 0; msr->write_val = 0;
msr->available = 1; msr->fault_expected = false;
break; break;
case 24: case 24:
msr->idx = HV_X64_MSR_STIMER0_CONFIG; msr->idx = HV_X64_MSR_STIMER0_CONFIG;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 25: case 25:
feat->eax |= HV_MSR_SYNTIMER_AVAILABLE; feat->eax |= HV_MSR_SYNTIMER_AVAILABLE;
msr->idx = HV_X64_MSR_STIMER0_CONFIG; msr->idx = HV_X64_MSR_STIMER0_CONFIG;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 26: case 26:
msr->idx = HV_X64_MSR_STIMER0_CONFIG; msr->idx = HV_X64_MSR_STIMER0_CONFIG;
msr->write = 1; msr->write = true;
msr->write_val = 0; msr->write_val = 0;
msr->available = 1; msr->fault_expected = false;
break; break;
case 27: case 27:
/* Direct mode test */ /* Direct mode test */
msr->idx = HV_X64_MSR_STIMER0_CONFIG; msr->idx = HV_X64_MSR_STIMER0_CONFIG;
msr->write = 1; msr->write = true;
msr->write_val = 1 << 12; msr->write_val = 1 << 12;
msr->available = 0; msr->fault_expected = true;
break; break;
case 28: case 28:
feat->edx |= HV_STIMER_DIRECT_MODE_AVAILABLE; feat->edx |= HV_STIMER_DIRECT_MODE_AVAILABLE;
msr->idx = HV_X64_MSR_STIMER0_CONFIG; msr->idx = HV_X64_MSR_STIMER0_CONFIG;
msr->write = 1; msr->write = true;
msr->write_val = 1 << 12; msr->write_val = 1 << 12;
msr->available = 1; msr->fault_expected = false;
break; break;
case 29: case 29:
msr->idx = HV_X64_MSR_EOI; msr->idx = HV_X64_MSR_EOI;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 30: case 30:
feat->eax |= HV_MSR_APIC_ACCESS_AVAILABLE; feat->eax |= HV_MSR_APIC_ACCESS_AVAILABLE;
msr->idx = HV_X64_MSR_EOI; msr->idx = HV_X64_MSR_EOI;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 1; msr->fault_expected = false;
break; break;
case 31: case 31:
msr->idx = HV_X64_MSR_TSC_FREQUENCY; msr->idx = HV_X64_MSR_TSC_FREQUENCY;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 32: case 32:
feat->eax |= HV_ACCESS_FREQUENCY_MSRS; feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
msr->idx = HV_X64_MSR_TSC_FREQUENCY; msr->idx = HV_X64_MSR_TSC_FREQUENCY;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 33: case 33:
/* Read only */ /* Read only */
msr->idx = HV_X64_MSR_TSC_FREQUENCY; msr->idx = HV_X64_MSR_TSC_FREQUENCY;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 0; msr->fault_expected = true;
break; break;
case 34: case 34:
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 35: case 35:
feat->eax |= HV_ACCESS_REENLIGHTENMENT; feat->eax |= HV_ACCESS_REENLIGHTENMENT;
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 36: case 36:
msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL; msr->idx = HV_X64_MSR_REENLIGHTENMENT_CONTROL;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 1; msr->fault_expected = false;
break; break;
case 37: case 37:
/* Can only write '0' */ /* Can only write '0' */
msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS; msr->idx = HV_X64_MSR_TSC_EMULATION_STATUS;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 0; msr->fault_expected = true;
break; break;
case 38: case 38:
msr->idx = HV_X64_MSR_CRASH_P0; msr->idx = HV_X64_MSR_CRASH_P0;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 39: case 39:
feat->edx |= HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE; feat->edx |= HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE;
msr->idx = HV_X64_MSR_CRASH_P0; msr->idx = HV_X64_MSR_CRASH_P0;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 40: case 40:
msr->idx = HV_X64_MSR_CRASH_P0; msr->idx = HV_X64_MSR_CRASH_P0;
msr->write = 1; msr->write = true;
msr->write_val = 1; msr->write_val = 1;
msr->available = 1; msr->fault_expected = false;
break; break;
case 41: case 41:
msr->idx = HV_X64_MSR_SYNDBG_STATUS; msr->idx = HV_X64_MSR_SYNDBG_STATUS;
msr->write = 0; msr->write = false;
msr->available = 0; msr->fault_expected = true;
break; break;
case 42: case 42:
feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE; feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
dbg->eax |= HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING; dbg->eax |= HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
msr->idx = HV_X64_MSR_SYNDBG_STATUS; msr->idx = HV_X64_MSR_SYNDBG_STATUS;
msr->write = 0; msr->write = false;
msr->available = 1; msr->fault_expected = false;
break; break;
case 43: case 43:
msr->idx = HV_X64_MSR_SYNDBG_STATUS; msr->idx = HV_X64_MSR_SYNDBG_STATUS;
msr->write = 1; msr->write = true;
msr->write_val = 0; msr->write_val = 0;
msr->available = 1; msr->fault_expected = false;
break; break;
case 44: case 44: