mtd: spi-nor: move all xilinx specifics into xilinx.c
Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
This commit is contained in:
Michael Walle
Tudor Ambarus
parent
9fb4beb1b0
commit
8b4195cd6d
@ -598,57 +598,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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return ret;
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}
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/**
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* spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @sr: pointer to a DMA-able buffer where the value of the
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* Status Register will be written.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, sr, 0));
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
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1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
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return ret;
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}
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/**
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* spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
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* the flash is ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int spi_nor_xsr_ready(struct spi_nor *nor)
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{
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int ret;
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ret = spi_nor_xread_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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return !!(nor->bouncebuf[0] & XSR_RDY);
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}
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/**
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* spi_nor_clear_sr() - Clear the Status Register.
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* @nor: pointer to 'struct spi_nor'.
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@ -798,10 +747,7 @@ static int spi_nor_ready(struct spi_nor *nor)
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if (nor->params->ready)
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return nor->params->ready(nor);
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if (nor->flags & SNOR_F_READY_XSR_RDY)
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sr = spi_nor_xsr_ready(nor);
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else
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sr = spi_nor_sr_ready(nor);
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sr = spi_nor_sr_ready(nor);
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if (sr < 0)
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return sr;
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fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
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@ -2677,14 +2623,6 @@ static void spi_nor_init_flags(struct spi_nor *nor)
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if (flags & USE_FSR)
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nor->flags |= SNOR_F_USE_FSR;
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/*
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* Make sure the XSR_RDY flag is set before calling
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* spi_nor_wait_till_ready(). Xilinx S3AN share MFR
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* with Atmel SPI NOR.
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*/
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if (flags & SPI_NOR_XSR_RDY)
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nor->flags |= SNOR_F_READY_XSR_RDY;
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}
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/**
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@ -15,7 +15,6 @@ enum spi_nor_option_flags {
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SNOR_F_USE_FSR = BIT(0),
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SNOR_F_HAS_SR_TB = BIT(1),
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SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
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SNOR_F_READY_XSR_RDY = BIT(3),
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SNOR_F_USE_CLSR = BIT(4),
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SNOR_F_BROKEN_RESET = BIT(5),
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SNOR_F_4B_OPCODES = BIT(6),
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@ -351,8 +350,6 @@ struct spi_nor_fixups {
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* SPI_NOR_NO_FR: can't do fastread.
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* USE_CLSR: use CLSR command.
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* USE_FSR: use flag status register
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* SPI_NOR_XSR_RDY: S3AN flashes have specific opcode to read the
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* status register.
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*
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* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
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* Used when SFDP tables are not defined in the flash. These
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@ -405,7 +402,6 @@ struct flash_info {
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#define SPI_NOR_NO_FR BIT(8)
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#define USE_CLSR BIT(9)
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#define USE_FSR BIT(10)
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#define SPI_NOR_XSR_RDY BIT(11)
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u8 no_sfdp_flags;
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#define SPI_NOR_SKIP_SFDP BIT(0)
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@ -462,19 +458,6 @@ struct flash_info {
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.addr_width = (_addr_width), \
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.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8 * (_page_size)), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
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#define OTP_INFO(_len, _n_regions, _base, _offset) \
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.otp_org = { \
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.len = (_len), \
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@ -564,7 +547,6 @@ int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
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int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
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int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
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int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
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ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
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u8 *buf);
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ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
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@ -8,6 +8,27 @@
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#include "core.h"
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#define SPINOR_OP_XSE 0x50 /* Sector erase */
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#define SPINOR_OP_XPP 0x82 /* Page program */
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#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
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#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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#define XSR_RDY BIT(7) /* Ready */
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8 * (_page_size)), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR
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/* Xilinx S3AN share MFR with Atmel SPI NOR */
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static const struct flash_info xilinx_nor_parts[] = {
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/* Xilinx S3AN Internal Flash */
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{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
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@ -38,6 +59,57 @@ static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
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return page | offset;
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}
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/**
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* spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @sr: pointer to a DMA-able buffer where the value of the
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* Status Register will be written.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(1, sr, 0));
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
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1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
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return ret;
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}
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/**
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* spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
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* the flash is ready for new commands.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int spi_nor_xsr_ready(struct spi_nor *nor)
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{
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int ret;
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ret = spi_nor_xread_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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return !!(nor->bouncebuf[0] & XSR_RDY);
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}
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static int xilinx_nor_setup(struct spi_nor *nor,
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const struct spi_nor_hwcaps *hwcaps)
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{
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@ -83,6 +155,7 @@ static int xilinx_nor_setup(struct spi_nor *nor,
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static void xilinx_nor_late_init(struct spi_nor *nor)
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{
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nor->params->setup = xilinx_nor_setup;
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nor->params->ready = spi_nor_xsr_ready;
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}
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static const struct spi_nor_fixups xilinx_nor_fixups = {
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@ -86,15 +86,6 @@
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#define SPINOR_OP_BP 0x02 /* Byte program */
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#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
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/* Used for S3AN flashes only */
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#define SPINOR_OP_XSE 0x50 /* Sector erase */
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#define SPINOR_OP_XPP 0x82 /* Page program */
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#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
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#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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#define XSR_RDY BIT(7) /* Ready */
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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