Merge branch 'x86/srbds' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 srbds fixes from Thomas Gleixner:
"The 9th episode of the dime novel "The performance killer" with the
subtitle "Slow Randomizing Boosts Denial of Service".
SRBDS is an MDS-like speculative side channel that can leak bits from
the random number generator (RNG) across cores and threads. New
microcode serializes the processor access during the execution of
RDRAND and RDSEED. This ensures that the shared buffer is overwritten
before it is released for reuse. This is equivalent to a full bus
lock, which means that many threads running the RNG instructions in
parallel have the same effect as the same amount of threads issuing a
locked instruction targeting an address which requires locking of two
cachelines at once.
The mitigation support comes with the usual pile of unpleasant
ingredients:
- command line options
- sysfs file
- microcode checks
- a list of vulnerable CPUs identified by model and stepping this
time which requires stepping match support for the cpu match logic.
- the inevitable slowdown of affected CPUs"
* branch 'x86/srbds' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/speculation: Add Ivy Bridge to affected list
x86/speculation: Add SRBDS vulnerability and mitigation documentation
x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation
x86/cpu: Add 'table' argument to cpu_matches()
This commit is contained in:
Linus Torvalds
commit
8b4d37db9a
@ -486,6 +486,7 @@ What: /sys/devices/system/cpu/vulnerabilities
|
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/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
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/sys/devices/system/cpu/vulnerabilities/l1tf
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/sys/devices/system/cpu/vulnerabilities/mds
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/sys/devices/system/cpu/vulnerabilities/srbds
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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Date: January 2018
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@ -14,3 +14,4 @@ are configurable at compile, boot or run time.
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mds
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tsx_async_abort
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multihit.rst
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special-register-buffer-data-sampling.rst
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@ -0,0 +1,149 @@
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.. SPDX-License-Identifier: GPL-2.0
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SRBDS - Special Register Buffer Data Sampling
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=============================================
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SRBDS is a hardware vulnerability that allows MDS :doc:`mds` techniques to
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infer values returned from special register accesses. Special register
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accesses are accesses to off core registers. According to Intel's evaluation,
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the special register reads that have a security expectation of privacy are
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RDRAND, RDSEED and SGX EGETKEY.
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When RDRAND, RDSEED and EGETKEY instructions are used, the data is moved
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to the core through the special register mechanism that is susceptible
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to MDS attacks.
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Affected processors
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--------------------
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Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED may
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be affected.
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A processor is affected by SRBDS if its Family_Model and stepping is
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in the following list, with the exception of the listed processors
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exporting MDS_NO while Intel TSX is available yet not enabled. The
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latter class of processors are only affected when Intel TSX is enabled
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by software using TSX_CTRL_MSR otherwise they are not affected.
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============= ============ ========
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common name Family_Model Stepping
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============= ============ ========
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IvyBridge 06_3AH All
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Haswell 06_3CH All
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Haswell_L 06_45H All
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Haswell_G 06_46H All
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Broadwell_G 06_47H All
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Broadwell 06_3DH All
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Skylake_L 06_4EH All
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Skylake 06_5EH All
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Kabylake_L 06_8EH <= 0xC
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Kabylake 06_9EH <= 0xD
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============= ============ ========
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Related CVEs
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------------
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The following CVE entry is related to this SRBDS issue:
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============== ===== =====================================
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CVE-2020-0543 SRBDS Special Register Buffer Data Sampling
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============== ===== =====================================
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Attack scenarios
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----------------
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An unprivileged user can extract values returned from RDRAND and RDSEED
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executed on another core or sibling thread using MDS techniques.
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Mitigation mechanism
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-------------------
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Intel will release microcode updates that modify the RDRAND, RDSEED, and
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EGETKEY instructions to overwrite secret special register data in the shared
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staging buffer before the secret data can be accessed by another logical
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processor.
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During execution of the RDRAND, RDSEED, or EGETKEY instructions, off-core
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accesses from other logical processors will be delayed until the special
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register read is complete and the secret data in the shared staging buffer is
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overwritten.
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This has three effects on performance:
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#. RDRAND, RDSEED, or EGETKEY instructions have higher latency.
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#. Executing RDRAND at the same time on multiple logical processors will be
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serialized, resulting in an overall reduction in the maximum RDRAND
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bandwidth.
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#. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
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logical processors that miss their core caches, with an impact similar to
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legacy locked cache-line-split accesses.
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The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
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the mitigation for RDRAND and RDSEED instructions executed outside of Intel
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Software Guard Extensions (Intel SGX) enclaves. On logical processors that
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disable the mitigation using this opt-out mechanism, RDRAND and RDSEED do not
|
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take longer to execute and do not impact performance of sibling logical
|
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processors memory accesses. The opt-out mechanism does not affect Intel SGX
|
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enclaves (including execution of RDRAND or RDSEED inside an enclave, as well
|
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as EGETKEY execution).
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IA32_MCU_OPT_CTRL MSR Definition
|
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--------------------------------
|
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Along with the mitigation for this issue, Intel added a new thread-scope
|
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IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
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RNGDS_MITG_DIS (bit 0) is enumerated by CPUID.(EAX=07H,ECX=0).EDX[SRBDS_CTRL =
|
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9]==1. This MSR is introduced through the microcode update.
|
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Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
|
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disables the mitigation for RDRAND and RDSEED executed outside of an Intel SGX
|
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enclave on that logical processor. Opting out of the mitigation for a
|
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particular logical processor does not affect the RDRAND and RDSEED mitigations
|
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for other logical processors.
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Note that inside of an Intel SGX enclave, the mitigation is applied regardless
|
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of the value of RNGDS_MITG_DS.
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Mitigation control on the kernel command line
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---------------------------------------------
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The kernel command line allows control over the SRBDS mitigation at boot time
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with the option "srbds=". The option for this is:
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============= =============================================================
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off This option disables SRBDS mitigation for RDRAND and RDSEED on
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affected platforms.
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============= =============================================================
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SRBDS System Information
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-----------------------
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The Linux kernel provides vulnerability status information through sysfs. For
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SRBDS this can be accessed by the following sysfs file:
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/sys/devices/system/cpu/vulnerabilities/srbds
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The possible values contained in this file are:
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============================== =============================================
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Not affected Processor not vulnerable
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Vulnerable Processor vulnerable and mitigation disabled
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Vulnerable: No microcode Processor vulnerable and microcode is missing
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mitigation
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Mitigation: Microcode Processor is vulnerable and mitigation is in
|
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effect.
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Mitigation: TSX disabled Processor is only vulnerable when TSX is
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enabled while this system was booted with TSX
|
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disabled.
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Unknown: Dependent on
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hypervisor status Running on virtual guest processor that is
|
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affected but with no way to know if host
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processor is mitigated or vulnerable.
|
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============================== =============================================
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SRBDS Default mitigation
|
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------------------------
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This new microcode serializes processor access during execution of RDRAND,
|
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RDSEED ensures that the shared buffer is overwritten before it is released for
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reuse. Use the "srbds=off" kernel command line to disable the mitigation for
|
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RDRAND and RDSEED.
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@ -4837,6 +4837,26 @@
|
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the kernel will oops in either "warn" or "fatal"
|
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mode.
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|
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srbds= [X86,INTEL]
|
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Control the Special Register Buffer Data Sampling
|
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(SRBDS) mitigation.
|
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|
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Certain CPUs are vulnerable to an MDS-like
|
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exploit which can leak bits from the random
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number generator.
|
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|
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By default, this issue is mitigated by
|
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microcode. However, the microcode fix can cause
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the RDRAND and RDSEED instructions to become
|
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much slower. Among other effects, this will
|
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result in reduced throughput from /dev/urandom.
|
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|
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The microcode mitigation can be disabled with
|
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the following option:
|
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|
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off: Disable mitigation and remove
|
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performance impact to RDRAND and RDSEED
|
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|
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srcutree.counter_wrap_check [KNL]
|
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Specifies how frequently to check for
|
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grace-period sequence counter wrap for the
|
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|
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@ -362,6 +362,7 @@
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
|
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#define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */
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#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
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#define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */
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#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
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#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
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#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
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@ -407,5 +408,6 @@
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#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
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#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
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#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
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#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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#endif /* _ASM_X86_CPUFEATURES_H */
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@ -128,6 +128,10 @@
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#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
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#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
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/* SRBDS support */
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#define MSR_IA32_MCU_OPT_CTRL 0x00000123
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#define RNGDS_MITG_DIS BIT(0)
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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#define MSR_IA32_SYSENTER_EIP 0x00000176
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@ -41,6 +41,7 @@ static void __init l1tf_select_mitigation(void);
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static void __init mds_select_mitigation(void);
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static void __init mds_print_mitigation(void);
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static void __init taa_select_mitigation(void);
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static void __init srbds_select_mitigation(void);
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/* The base value of the SPEC_CTRL MSR that always has to be preserved. */
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u64 x86_spec_ctrl_base;
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@ -108,6 +109,7 @@ void __init check_bugs(void)
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l1tf_select_mitigation();
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mds_select_mitigation();
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taa_select_mitigation();
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srbds_select_mitigation();
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/*
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* As MDS and TAA mitigations are inter-related, print MDS
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@ -397,6 +399,97 @@ static int __init tsx_async_abort_parse_cmdline(char *str)
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}
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early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
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#undef pr_fmt
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#define pr_fmt(fmt) "SRBDS: " fmt
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enum srbds_mitigations {
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SRBDS_MITIGATION_OFF,
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SRBDS_MITIGATION_UCODE_NEEDED,
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SRBDS_MITIGATION_FULL,
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SRBDS_MITIGATION_TSX_OFF,
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SRBDS_MITIGATION_HYPERVISOR,
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};
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static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
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|
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static const char * const srbds_strings[] = {
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[SRBDS_MITIGATION_OFF] = "Vulnerable",
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[SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
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[SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
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[SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
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[SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
|
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};
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|
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static bool srbds_off;
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|
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void update_srbds_msr(void)
|
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{
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u64 mcu_ctrl;
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|
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if (!boot_cpu_has_bug(X86_BUG_SRBDS))
|
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return;
|
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|
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if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
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return;
|
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|
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if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
|
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return;
|
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|
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rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
|
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|
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switch (srbds_mitigation) {
|
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case SRBDS_MITIGATION_OFF:
|
||||
case SRBDS_MITIGATION_TSX_OFF:
|
||||
mcu_ctrl |= RNGDS_MITG_DIS;
|
||||
break;
|
||||
case SRBDS_MITIGATION_FULL:
|
||||
mcu_ctrl &= ~RNGDS_MITG_DIS;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
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wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
|
||||
}
|
||||
|
||||
static void __init srbds_select_mitigation(void)
|
||||
{
|
||||
u64 ia32_cap;
|
||||
|
||||
if (!boot_cpu_has_bug(X86_BUG_SRBDS))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Check to see if this is one of the MDS_NO systems supporting
|
||||
* TSX that are only exposed to SRBDS when TSX is enabled.
|
||||
*/
|
||||
ia32_cap = x86_read_arch_cap_msr();
|
||||
if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
|
||||
srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
|
||||
else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
||||
srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
|
||||
else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
|
||||
srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
|
||||
else if (cpu_mitigations_off() || srbds_off)
|
||||
srbds_mitigation = SRBDS_MITIGATION_OFF;
|
||||
|
||||
update_srbds_msr();
|
||||
pr_info("%s\n", srbds_strings[srbds_mitigation]);
|
||||
}
|
||||
|
||||
static int __init srbds_parse_cmdline(char *str)
|
||||
{
|
||||
if (!str)
|
||||
return -EINVAL;
|
||||
|
||||
if (!boot_cpu_has_bug(X86_BUG_SRBDS))
|
||||
return 0;
|
||||
|
||||
srbds_off = !strcmp(str, "off");
|
||||
return 0;
|
||||
}
|
||||
early_param("srbds", srbds_parse_cmdline);
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "Spectre V1 : " fmt
|
||||
|
||||
@ -1528,6 +1621,11 @@ static char *ibpb_state(void)
|
||||
return "";
|
||||
}
|
||||
|
||||
static ssize_t srbds_show_state(char *buf)
|
||||
{
|
||||
return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
|
||||
}
|
||||
|
||||
static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
|
||||
char *buf, unsigned int bug)
|
||||
{
|
||||
@ -1572,6 +1670,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
|
||||
case X86_BUG_ITLB_MULTIHIT:
|
||||
return itlb_multihit_show_state(buf);
|
||||
|
||||
case X86_BUG_SRBDS:
|
||||
return srbds_show_state(buf);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -1618,4 +1719,9 @@ ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr
|
||||
{
|
||||
return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
|
||||
}
|
||||
|
||||
ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
|
||||
{
|
||||
return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1073,9 +1073,30 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
|
||||
{}
|
||||
};
|
||||
|
||||
static bool __init cpu_matches(unsigned long which)
|
||||
#define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
|
||||
X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
|
||||
INTEL_FAM6_##model, steppings, \
|
||||
X86_FEATURE_ANY, issues)
|
||||
|
||||
#define SRBDS BIT(0)
|
||||
|
||||
static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
|
||||
VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
|
||||
VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
|
||||
{}
|
||||
};
|
||||
|
||||
static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
|
||||
{
|
||||
const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
|
||||
const struct x86_cpu_id *m = x86_match_cpu(table);
|
||||
|
||||
return m && !!(m->driver_data & which);
|
||||
}
|
||||
@ -1095,31 +1116,34 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
|
||||
u64 ia32_cap = x86_read_arch_cap_msr();
|
||||
|
||||
/* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
|
||||
if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
|
||||
if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
|
||||
!(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
|
||||
setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
|
||||
|
||||
if (cpu_matches(NO_SPECULATION))
|
||||
if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
|
||||
return;
|
||||
|
||||
setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
|
||||
|
||||
if (!cpu_matches(NO_SPECTRE_V2))
|
||||
if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
|
||||
setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
|
||||
|
||||
if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
|
||||
if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
|
||||
!(ia32_cap & ARCH_CAP_SSB_NO) &&
|
||||
!cpu_has(c, X86_FEATURE_AMD_SSB_NO))
|
||||
setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
|
||||
|
||||
if (ia32_cap & ARCH_CAP_IBRS_ALL)
|
||||
setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
|
||||
|
||||
if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
|
||||
if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
|
||||
!(ia32_cap & ARCH_CAP_MDS_NO)) {
|
||||
setup_force_cpu_bug(X86_BUG_MDS);
|
||||
if (cpu_matches(MSBDS_ONLY))
|
||||
if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
|
||||
setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
|
||||
}
|
||||
|
||||
if (!cpu_matches(NO_SWAPGS))
|
||||
if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
|
||||
setup_force_cpu_bug(X86_BUG_SWAPGS);
|
||||
|
||||
/*
|
||||
@ -1137,7 +1161,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
|
||||
(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
|
||||
setup_force_cpu_bug(X86_BUG_TAA);
|
||||
|
||||
if (cpu_matches(NO_MELTDOWN))
|
||||
/*
|
||||
* SRBDS affects CPUs which support RDRAND or RDSEED and are listed
|
||||
* in the vulnerability blacklist.
|
||||
*/
|
||||
if ((cpu_has(c, X86_FEATURE_RDRAND) ||
|
||||
cpu_has(c, X86_FEATURE_RDSEED)) &&
|
||||
cpu_matches(cpu_vuln_blacklist, SRBDS))
|
||||
setup_force_cpu_bug(X86_BUG_SRBDS);
|
||||
|
||||
if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
|
||||
return;
|
||||
|
||||
/* Rogue Data Cache Load? No! */
|
||||
@ -1146,7 +1179,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
|
||||
|
||||
setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
|
||||
|
||||
if (cpu_matches(NO_L1TF))
|
||||
if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
|
||||
return;
|
||||
|
||||
setup_force_cpu_bug(X86_BUG_L1TF);
|
||||
@ -1574,6 +1607,7 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c)
|
||||
mtrr_ap_init();
|
||||
validate_apic_and_package_id(c);
|
||||
x86_spec_ctrl_setup_ap();
|
||||
update_srbds_msr();
|
||||
}
|
||||
|
||||
static __init int setup_noclflush(char *arg)
|
||||
|
||||
@ -77,6 +77,7 @@ extern void detect_ht(struct cpuinfo_x86 *c);
|
||||
unsigned int aperfmperf_get_khz(int cpu);
|
||||
|
||||
extern void x86_spec_ctrl_setup_ap(void);
|
||||
extern void update_srbds_msr(void);
|
||||
|
||||
extern u64 x86_read_arch_cap_msr(void);
|
||||
|
||||
|
||||
@ -562,6 +562,12 @@ ssize_t __weak cpu_show_itlb_multihit(struct device *dev,
|
||||
return sprintf(buf, "Not affected\n");
|
||||
}
|
||||
|
||||
ssize_t __weak cpu_show_srbds(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
return sprintf(buf, "Not affected\n");
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
|
||||
static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
|
||||
static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
|
||||
@ -570,6 +576,7 @@ static DEVICE_ATTR(l1tf, 0444, cpu_show_l1tf, NULL);
|
||||
static DEVICE_ATTR(mds, 0444, cpu_show_mds, NULL);
|
||||
static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL);
|
||||
static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL);
|
||||
static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL);
|
||||
|
||||
static struct attribute *cpu_root_vulnerabilities_attrs[] = {
|
||||
&dev_attr_meltdown.attr,
|
||||
@ -580,6 +587,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = {
|
||||
&dev_attr_mds.attr,
|
||||
&dev_attr_tsx_async_abort.attr,
|
||||
&dev_attr_itlb_multihit.attr,
|
||||
&dev_attr_srbds.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user