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arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode

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DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay
Value is not present in the device tree. Thus, add Itap Delay Value
for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC
according to datasheet for J784s4.

[+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in
	J784s4 datasheet
- https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf

Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Reviewed-by: Judith Mendez <jm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20231201082045.790478-4-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Bhavya Kapoor 2023-12-01 13:50:45 +05:30 committed by Nishanth Menon
parent 4a52a82085
commit 8bbe8a7dba
1 changed files with 1 additions and 0 deletions
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arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
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@ -712,6 +712,7 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;