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misc: lattice-ecp3-config: Remove set but clearly unused variable 'ret'

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It's odd for the return value to be assigned to a variable so many
times, but never actually checked, but this has been the case since
the driver's inception in 2012.  If it hasn't caused any issues by
now, it's probably unlikely to.  Let's take it out, at least until
someone finds a reason to start using it.

Fixes the following W=1 kernel build warning:

 drivers/misc/lattice-ecp3-config.c: In function ‘firmware_load’:
 drivers/misc/lattice-ecp3-config.c:70:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable]
 70 | int ret;
 | ^~~

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200701085853.164358-13-lee.jones@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Lee Jones 2020-07-01 09:58:45 +01:00 committed by Greg Kroah-Hartman
parent 82f5b473d9
commit 8bc056e84a
1 changed files with 9 additions and 10 deletions
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19
drivers/misc/lattice-ecp3-config.c
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@ -67,7 +67,6 @@ static void firmware_load(const struct firmware *fw, void *context)
struct spi_device *spi = (struct spi_device *)context; struct spi_device *spi = (struct spi_device *)context;
struct fpga_data *data = spi_get_drvdata(spi); struct fpga_data *data = spi_get_drvdata(spi);
u8 *buffer; u8 *buffer;
int ret;
u8 txbuf[8]; u8 txbuf[8];
u8 rxbuf[8]; u8 rxbuf[8];
int rx_len = 8; int rx_len = 8;
@ -92,7 +91,7 @@ static void firmware_load(const struct firmware *fw, void *context)
/* Trying to speak with the FPGA via SPI... */ /* Trying to speak with the FPGA via SPI... */
txbuf[0] = FPGA_CMD_READ_ID; txbuf[0] = FPGA_CMD_READ_ID;
ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
jedec_id = get_unaligned_be32(&rxbuf[4]); jedec_id = get_unaligned_be32(&rxbuf[4]);
dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
@ -110,7 +109,7 @@ static void firmware_load(const struct firmware *fw, void *context)
dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name); dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
txbuf[0] = FPGA_CMD_READ_STATUS; txbuf[0] = FPGA_CMD_READ_STATUS;
ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
status = get_unaligned_be32(&rxbuf[4]); status = get_unaligned_be32(&rxbuf[4]);
dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
@ -130,20 +129,20 @@ static void firmware_load(const struct firmware *fw, void *context)
memcpy(buffer + 4, fw->data, fw->size); memcpy(buffer + 4, fw->data, fw->size);
txbuf[0] = FPGA_CMD_REFRESH; txbuf[0] = FPGA_CMD_REFRESH;
ret = spi_write(spi, txbuf, 4); spi_write(spi, txbuf, 4);
txbuf[0] = FPGA_CMD_WRITE_EN; txbuf[0] = FPGA_CMD_WRITE_EN;
ret = spi_write(spi, txbuf, 4); spi_write(spi, txbuf, 4);
txbuf[0] = FPGA_CMD_CLEAR; txbuf[0] = FPGA_CMD_CLEAR;
ret = spi_write(spi, txbuf, 4); spi_write(spi, txbuf, 4);
/* /*
* Wait for FPGA memory to become cleared * Wait for FPGA memory to become cleared
*/ */
for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) { for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
txbuf[0] = FPGA_CMD_READ_STATUS; txbuf[0] = FPGA_CMD_READ_STATUS;
ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
status = get_unaligned_be32(&rxbuf[4]); status = get_unaligned_be32(&rxbuf[4]);
if (status == FPGA_STATUS_CLEARED) if (status == FPGA_STATUS_CLEARED)
break; break;
@ -160,13 +159,13 @@ static void firmware_load(const struct firmware *fw, void *context)
} }
dev_info(&spi->dev, "Configuring the FPGA...\n"); dev_info(&spi->dev, "Configuring the FPGA...\n");
ret = spi_write(spi, buffer, fw->size + 8); spi_write(spi, buffer, fw->size + 8);
txbuf[0] = FPGA_CMD_WRITE_DIS; txbuf[0] = FPGA_CMD_WRITE_DIS;
ret = spi_write(spi, txbuf, 4); spi_write(spi, txbuf, 4);
txbuf[0] = FPGA_CMD_READ_STATUS; txbuf[0] = FPGA_CMD_READ_STATUS;
ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
status = get_unaligned_be32(&rxbuf[4]); status = get_unaligned_be32(&rxbuf[4]);
dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);