staging: r8188eu: support only us in PWR_CMD_DELAY
PWR_CMD_DELAY has only a single remaining user, who needs a delay in us. Remove the code and defines for delays in ms. Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> # Edimax N150 Signed-off-by: Martin Kaiser <martin@kaiser.cx> Link: https://lore.kernel.org/r/20220704145221.159949-3-martin@kaiser.cx Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -20,20 +20,15 @@
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/* } while (not timeout); */
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#define PWR_CMD_DELAY 0x03
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/* offset: the value to delay */
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/* offset: the value to delay (in us) */
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/* msk: N/A */
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/* value: the unit of delay, 0: us, 1: ms */
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/* value: N/A */
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#define PWR_CMD_END 0x04
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/* offset: N/A */
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/* msk: N/A */
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/* value: N/A */
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enum pwrseq_cmd_delat_unit {
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PWRSEQ_DELAY_US,
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PWRSEQ_DELAY_MS,
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};
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struct wl_pwr_cfg {
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u16 offset;
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u8 cmd:4;
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@ -79,7 +74,7 @@ static struct wl_pwr_cfg rtl8188E_enter_lps_flow[] = {
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{ 0x05FA, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
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{ 0x05FB, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */
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{ 0x0002, PWR_CMD_WRITE, BIT(0), 0 }, /* CCK and OFDM are disabled, clocks are gated */
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{ 0x0002, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US },
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{ 0x0002, PWR_CMD_DELAY, 0, 0 },
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{ 0x0100, PWR_CMD_WRITE, 0xFF, 0x3F }, /* Reset MAC TRX */
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{ 0x0101, PWR_CMD_WRITE, BIT(1), 0 }, /* check if removed later */
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{ 0x0553, PWR_CMD_WRITE, BIT(5), BIT(5) }, /* Respond TxOK to scheduler */
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@ -149,10 +144,7 @@ u8 HalPwrSeqCmdParsing(struct adapter *padapter, enum r8188eu_pwr_seq seq)
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} while (!poll_bit);
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break;
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case PWR_CMD_DELAY:
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if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
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udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
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else
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udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd) * 1000);
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udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd));
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break;
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case PWR_CMD_END:
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/* When this command is parsed, end the process */
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