microblaze_v8: cache support
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek
parent
37069abf29
commit
8beb8503bf
45
arch/microblaze/include/asm/cache.h
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45
arch/microblaze/include/asm/cache.h
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/*
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* Cache operations
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_CACHE_H
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#define _ASM_MICROBLAZE_CACHE_H
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#include <asm/registers.h>
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#define L1_CACHE_SHIFT 2
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/* word-granular cache in microblaze */
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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void _enable_icache(void);
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void _disable_icache(void);
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void _invalidate_icache(unsigned int addr);
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#define __enable_icache() _enable_icache()
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#define __disable_icache() _disable_icache()
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#define __invalidate_icache(addr) _invalidate_icache(addr)
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void _enable_dcache(void);
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void _disable_dcache(void);
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void _invalidate_dcache(unsigned int addr);
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#define __enable_dcache() _enable_dcache()
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#define __disable_dcache() _disable_dcache()
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#define __invalidate_dcache(addr) _invalidate_dcache(addr)
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/* FIXME - I don't think this is right */
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#ifdef CONFIG_XILINX_UNCACHED_SHADOW
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#define UNCACHED_SHADOW_MASK (CONFIG_XILINX_ERAM_SIZE)
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#endif
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#endif /* _ASM_MICROBLAZE_CACHE_H */
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85
arch/microblaze/include/asm/cacheflush.h
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arch/microblaze/include/asm/cacheflush.h
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/*
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* Copyright (C) 2007 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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* based on v850 version which was
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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*/
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#ifndef _ASM_MICROBLAZE_CACHEFLUSH_H
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#define _ASM_MICROBLAZE_CACHEFLUSH_H
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/* Somebody depends on this; sigh... */
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#include <linux/mm.h>
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/*
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* Cache handling functions.
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* Microblaze has a write-through data cache, meaning that the data cache
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* never needs to be flushed. The only flushing operations that are
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* implemented are to invalidate the instruction cache. These are called
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* after loading a user application into memory, we must invalidate the
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* instruction cache to make sure we don't fetch old, bad code.
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*/
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/* FIXME for LL-temac driver */
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#define invalidate_dcache_range(start, end) \
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__invalidate_dcache_range(start, end)
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#define flush_cache_all() __invalidate_cache_all()
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) __invalidate_cache_all()
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_range(start, end) __invalidate_dcache_range(start, end)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, len) __invalidate_icache_range(start, len)
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#define flush_icache_page(vma, pg) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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struct page;
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struct mm_struct;
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struct vm_area_struct;
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/* see arch/microblaze/kernel/cache.c */
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extern void __invalidate_icache_all(void);
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extern void __invalidate_icache_range(unsigned long start, unsigned long end);
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extern void __invalidate_icache_page(struct vm_area_struct *vma,
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struct page *page);
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extern void __invalidate_icache_user_range(struct vm_area_struct *vma,
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struct page *page,
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unsigned long adr, int len);
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extern void __invalidate_cache_sigtramp(unsigned long addr);
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extern void __invalidate_dcache_all(void);
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extern void __invalidate_dcache_range(unsigned long start, unsigned long end);
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extern void __invalidate_dcache_page(struct vm_area_struct *vma,
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struct page *page);
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extern void __invalidate_dcache_user_range(struct vm_area_struct *vma,
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struct page *page,
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unsigned long adr, int len);
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extern inline void __invalidate_cache_all(void)
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{
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__invalidate_icache_all();
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__invalidate_dcache_all();
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}
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy((dst), (src), (len)); \
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flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy((dst), (src), (len))
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#endif /* _ASM_MICROBLAZE_CACHEFLUSH_H */
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258
arch/microblaze/kernel/cpu/cache.c
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258
arch/microblaze/kernel/cpu/cache.c
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/*
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* Cache control for MicroBlaze cache memories
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <john.williams@petalogix.com>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <asm/cacheflush.h>
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#include <linux/cache.h>
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#include <asm/cpuinfo.h>
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/* Exported functions */
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void _enable_icache(void)
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{
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if (cpuinfo.use_icache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrset r0, %0; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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ori r12, r12, %0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory", "r12");
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#endif
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}
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}
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void _disable_icache(void)
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{
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if (cpuinfo.use_icache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrclr r0, %0; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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andi r12, r12, ~%0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_ICE) \
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: "memory", "r12");
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#endif
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}
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}
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void _invalidate_icache(unsigned int addr)
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{
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if (cpuinfo.use_icache) {
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__asm__ __volatile__ (" \
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wic %0, r0" \
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: \
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: "r" (addr));
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}
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}
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void _enable_dcache(void)
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{
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if (cpuinfo.use_dcache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrset r0, %0; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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ori r12, r12, %0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory", "r12");
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#endif
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}
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}
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void _disable_dcache(void)
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{
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if (cpuinfo.use_dcache) {
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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__asm__ __volatile__ (" \
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msrclr r0, %0; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory");
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#else
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__asm__ __volatile__ (" \
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mfs r12, rmsr; \
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nop; \
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andi r12, r12, ~%0; \
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mts rmsr, r12; \
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nop; " \
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: \
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: "i" (MSR_DCE) \
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: "memory", "r12");
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#endif
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}
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}
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void _invalidate_dcache(unsigned int addr)
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{
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if (cpuinfo.use_dcache)
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__asm__ __volatile__ (" \
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wdc %0, r0" \
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: \
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: "r" (addr));
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}
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void __invalidate_icache_all(void)
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{
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unsigned int i;
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unsigned flags;
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if (cpuinfo.use_icache) {
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local_irq_save(flags);
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__disable_icache();
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/* Just loop through cache size and invalidate, no need to add
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CACHE_BASE address */
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for (i = 0; i < cpuinfo.icache_size;
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i += cpuinfo.icache_line)
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__invalidate_icache(i);
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__enable_icache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_icache_range(unsigned long start, unsigned long end)
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{
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unsigned int i;
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unsigned flags;
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unsigned int align;
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if (cpuinfo.use_icache) {
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/*
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* No need to cover entire cache range,
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* just cover cache footprint
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*/
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end = min(start + cpuinfo.icache_size, end);
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align = ~(cpuinfo.icache_line - 1);
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start &= align; /* Make sure we are aligned */
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/* Push end up to the next cache line */
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end = ((end & align) + cpuinfo.icache_line);
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local_irq_save(flags);
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__disable_icache();
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for (i = start; i < end; i += cpuinfo.icache_line)
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__invalidate_icache(i);
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__enable_icache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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__invalidate_icache_all();
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}
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void __invalidate_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long adr,
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int len)
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{
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__invalidate_icache_all();
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}
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void __invalidate_cache_sigtramp(unsigned long addr)
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{
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__invalidate_icache_range(addr, addr + 8);
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}
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void __invalidate_dcache_all(void)
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{
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unsigned int i;
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unsigned flags;
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if (cpuinfo.use_dcache) {
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local_irq_save(flags);
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__disable_dcache();
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/*
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* Just loop through cache size and invalidate,
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* no need to add CACHE_BASE address
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*/
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for (i = 0; i < cpuinfo.dcache_size;
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i += cpuinfo.dcache_line)
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__invalidate_dcache(i);
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__enable_dcache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned int i;
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unsigned flags;
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unsigned int align;
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if (cpuinfo.use_dcache) {
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/*
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* No need to cover entire cache range,
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* just cover cache footprint
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*/
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end = min(start + cpuinfo.dcache_size, end);
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align = ~(cpuinfo.dcache_line - 1);
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start &= align; /* Make sure we are aligned */
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/* Push end up to the next cache line */
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end = ((end & align) + cpuinfo.dcache_line);
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local_irq_save(flags);
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__disable_dcache();
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for (i = start; i < end; i += cpuinfo.dcache_line)
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__invalidate_dcache(i);
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__enable_dcache();
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local_irq_restore(flags);
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}
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}
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void __invalidate_dcache_page(struct vm_area_struct *vma, struct page *page)
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{
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__invalidate_dcache_all();
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}
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void __invalidate_dcache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long adr,
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int len)
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{
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__invalidate_dcache_all();
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}
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