A collection of fixes that would be good to get merged before -rc1.
- Make of_clk.h self contained - Fix new qcom DT bindings that just merged to match the DTS files - Fix qcom clk driver to properly detect DFS clk frequencies - Fix the ls1028a driver to not deref a pointer before assigning it -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl48WfERHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWtnw/+P0xw3S0Wdkr4UEkfCmSf8/JAP6xXc4Of TFeJoXTCqqvgq66BpFVRMSPvA7jr2hx4siHBJbpXT4M+VpGhw5sRcEumQChHtZpX WDSUszR86hxQCyq4ONdU0hQ6YfL/Erx14WqAK/DMHMLUtqIbSkfeVlZNTqpBHrBk Nyx9S4rG0RerddmI1DPPikx3oPCwVxi+biqX3H+T1Ndsn2L/Iol+jerRfa9kbjRU kaH/gXByikMKt+EdKlVLoCEl9jOC9gDu3MvM5ik01pFF5+SVeUD89wSDRHjuyVf/ mfag7xwXxxbjQNYJdEJu3keZslzezBUDY1DDnxIXstA7NhaQp2Jw6CX1S+S4KszR Bh21okQGgSZUsnOVJmOOweqCPh8cvfyLb0sDjYlTgUog2QcQmBQbkTVqV5ZvvtF6 e5cdcxI7zHZQ5tszFXYk32GkXqN7QcucYy6HYbh6fcivkJOE5DozOUOP8DDkoP39 fWRCZiZLM3bWYx3he2MnMpZMxo7sLAMwpO2v+jxtqTZFVfvBPYaITuM08t+o9YH1 D+hIuSXoDKDzliQYEmo7p2k+JHstTw91sBuH9NRgNhcUZ1z/Fg8osfW7uBnuu5qv vpK/xZJo8zJF3046xlnaRDz/oO2VKv6Wvq/04ayE087MEKps6OxE9AwxreB3brj1 kPWlYe0uexQ= =fchl -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A collection of fixes: - Make of_clk.h self contained - Fix new qcom DT bindings that just merged to match the DTS files - Fix qcom clk driver to properly detect DFS clk frequencies - Fix the ls1028a driver to not deref a pointer before assigning it" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: of: clk: Make <linux/of_clk.h> self-contained clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for videocc-sc7180 dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180 clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for gpucc-sc7180 dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks clk: qcom: Get rid of the test clock for dispcc-sc7180 clk: qcom: Get rid of fallback global names for dispcc-sc7180 dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180 clk: qcom: rcg2: Don't crash if our parent can't be found; return an error clk: ls1028a: fix a dereference of pointer 'parent' before a null check dt-bindings: clk: qcom: Fix self-validation, split, and clean cruft clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq()
This commit is contained in:
Linus Torvalds
commit
8bf5973a4e
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8064.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'#thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on IPQ8074.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq8074
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-ipq8074";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8996.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8996.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8996
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Second XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cxo
|
||||
- const: cxo2
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x300000 0x90000>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8998.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8998
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: USB 3.0 phy pipe clock
|
||||
- description: UFS phy rx symbol clock for pipe 0
|
||||
- description: UFS phy rx symbol clock for pipe 1
|
||||
- description: UFS phy tx symbol clock
|
||||
- description: PCIE phy pipe clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: usb3_pipe
|
||||
- const: ufs_rx_symbol0
|
||||
- const: ufs_rx_symbol1
|
||||
- const: ufs_tx_symbol0
|
||||
- const: pcie0_pipe
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-msm8998";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x00100000 0xb0000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "xo",
|
||||
"sleep_clk",
|
||||
"usb3_pipe",
|
||||
"ufs_rx_symbol0",
|
||||
"ufs_rx_symbol1",
|
||||
"ufs_tx_symbol0",
|
||||
"pcie0_pipe";
|
||||
};
|
||||
...
|
||||
51
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
Normal file
51
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on QCS404.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-qcs404.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-qcs404
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-qcs404";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
75
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
Normal file
75
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc7180
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
72
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
Normal file
72
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8150
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8150.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8150.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8150
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -14,77 +14,42 @@ description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8994.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
- dt-bindings/clock/qcom,gcc-sdm845.h
|
||||
|
||||
properties:
|
||||
compatible :
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-apq8064
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-ipq8074
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-msm8994
|
||||
- qcom,gcc-msm8996
|
||||
- qcom,gcc-msm8998
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-qcs404
|
||||
- qcom,gcc-sc7180
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
- qcom,gcc-sdm845
|
||||
- qcom,gcc-sm8150
|
||||
|
||||
clocks:
|
||||
oneOf:
|
||||
#qcom,gcc-sm8150
|
||||
#qcom,gcc-sc7180
|
||||
- items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
#qcom,gcc-msm8996
|
||||
- items:
|
||||
- description: XO source
|
||||
- description: Second XO source
|
||||
- description: Sleep clock source
|
||||
#qcom,gcc-msm8998
|
||||
- items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: USB 3.0 phy pipe clock
|
||||
- description: UFS phy rx symbol clock for pipe 0
|
||||
- description: UFS phy rx symbol clock for pipe 1
|
||||
- description: UFS phy tx symbol clock
|
||||
- description: PCIE phy pipe clock
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
#qcom,gcc-sm8150
|
||||
#qcom,gcc-sc7180
|
||||
- items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
#qcom,gcc-msm8996
|
||||
- items:
|
||||
- const: cxo
|
||||
- const: cxo2
|
||||
- const: sleep_clk
|
||||
#qcom,gcc-msm8998
|
||||
- items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: usb3_pipe
|
||||
- const: ufs_rx_symbol0
|
||||
- const: ufs_rx_symbol1
|
||||
- const: ufs_tx_symbol0
|
||||
- const: pcie0_pipe
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-msm8994
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
- qcom,gcc-sdm845
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -98,31 +63,9 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Names for each nvmem-cells specified.
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -131,33 +74,6 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
then:
|
||||
required:
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,gcc-msm8998
|
||||
- qcom,gcc-sm8150
|
||||
- qcom,gcc-sc7180
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
@ -168,78 +84,4 @@ examples:
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
# Example of GCC with TSENS properties:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with protected-clocks properties:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
protected-clocks = <187>, <188>, <189>, <190>, <191>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock node properties for SM8150:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock nodes properties for SC7180:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>, <0>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of MSM8998 GCC:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-msm8998";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x00100000 0xb0000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "xo",
|
||||
"sleep_clk",
|
||||
"usb3_pipe",
|
||||
"ufs_rx_symbol0",
|
||||
"ufs_rx_symbol1",
|
||||
"ufs_tx_symbol0",
|
||||
"pcie0_pipe";
|
||||
};
|
||||
...
|
||||
|
||||
@ -1,72 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm grpahics clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,msm8998-gpucc
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sdm845-gpucc
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source from GCC(gcc_gpu_gpll0_clk_src)
|
||||
- description: GPLL0 div branch source from GCC(gcc_gpu_gpll0_div_clk_src)
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: xo
|
||||
- const: gpll0_main
|
||||
- const: gpll0_div
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
# Example of GPUCC with clock node properties for SDM845:
|
||||
- |
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sdm845-gpucc";
|
||||
reg = <0x5090000 0x9000>;
|
||||
clocks = <&rpmhcc 0>, <&gcc 31>, <&gcc 32>;
|
||||
clock-names = "xo", "gpll0_main", "gpll0_div";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -1,30 +1,28 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-msm8998.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-dispcc
|
||||
- qcom,sdm845-dispcc
|
||||
const: qcom,msm8998-gpucc
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -53,15 +51,16 @@ required:
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
# Example of DISPCC with clock node properties for SDM845:
|
||||
- |
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sdm845-dispcc";
|
||||
reg = <0xaf00000 0x10000>;
|
||||
clocks = <&rpmhcc 0>, <&gcc 24>;
|
||||
clock-names = "xo", "gpll0";
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@5065000 {
|
||||
compatible = "qcom,msm8998-gpucc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
reg = <0x05065000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>;
|
||||
clock-names = "xo", "gpll0";
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sc7180-dispcc";
|
||||
reg = <0 0x0af00000 0 0x200000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sc7180-gpucc";
|
||||
reg = <0 0x05090000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,videocc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ab00000 {
|
||||
compatible = "qcom,sc7180-videocc";
|
||||
reg = <0 0x0ab00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dispcc
|
||||
|
||||
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
|
||||
# The code had to use hardcoded mechanisms to find the input clocks.
|
||||
# New dts files should have these clocks.
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL0 div source from GCC
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: gcc_disp_gpll0_div_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dsi1_phy_pll_out_byteclk
|
||||
- const: dsi1_phy_pll_out_dsiclk
|
||||
- const: dp_link_clk_divsel_ten
|
||||
- const: dp_vco_divided_clk_src_mux
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sdm845-dispcc";
|
||||
reg = <0 0x0af00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"gcc_disp_gpll0_div_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dsi1_phy_pll_out_byteclk",
|
||||
"dsi1_phy_pll_out_dsiclk",
|
||||
"dp_link_clk_divsel_ten",
|
||||
"dp_vco_divided_clk_src_mux";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sdm845-gpucc";
|
||||
reg = <0 0x05090000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -1,30 +1,31 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller Binding
|
||||
title: Qualcomm Video Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,videocc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sdm845-videocc
|
||||
const: qcom,sdm845-videocc
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -48,15 +49,15 @@ required:
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
# Example of VIDEOCC with clock node properties for SDM845:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ab00000 {
|
||||
compatible = "qcom,sdm845-videocc";
|
||||
reg = <0xab00000 0x10000>;
|
||||
clocks = <&rpmhcc 0>;
|
||||
clock-names = "xo";
|
||||
reg = <0 0x0ab00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -187,7 +187,7 @@ static int plldig_init(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_plldig *data = to_clk_plldig(hw);
|
||||
struct clk_hw *parent = clk_hw_get_parent(hw);
|
||||
unsigned long parent_rate = clk_hw_get_rate(parent);
|
||||
unsigned long parent_rate;
|
||||
unsigned long val;
|
||||
unsigned long long lltmp;
|
||||
unsigned int mfd, fracdiv = 0;
|
||||
@ -195,6 +195,8 @@ static int plldig_init(struct clk_hw *hw)
|
||||
if (!parent)
|
||||
return -EINVAL;
|
||||
|
||||
parent_rate = clk_hw_get_rate(parent);
|
||||
|
||||
if (data->vco_freq) {
|
||||
mfd = data->vco_freq / parent_rate;
|
||||
lltmp = data->vco_freq % parent_rate;
|
||||
|
||||
@ -218,6 +218,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
|
||||
|
||||
clk_flags = clk_hw_get_flags(hw);
|
||||
p = clk_hw_get_parent_by_index(hw, index);
|
||||
if (!p)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk_flags & CLK_SET_RATE_PARENT) {
|
||||
rate = f->freq;
|
||||
if (f->pre_div) {
|
||||
@ -953,7 +956,7 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
struct clk_hw *p;
|
||||
unsigned long prate = 0;
|
||||
u32 val, mask, cfg, mode;
|
||||
u32 val, mask, cfg, mode, src;
|
||||
int i, num_parents;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
|
||||
@ -963,12 +966,12 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
|
||||
if (cfg & mask)
|
||||
f->pre_div = cfg & mask;
|
||||
|
||||
cfg &= CFG_SRC_SEL_MASK;
|
||||
cfg >>= CFG_SRC_SEL_SHIFT;
|
||||
src = cfg & CFG_SRC_SEL_MASK;
|
||||
src >>= CFG_SRC_SEL_SHIFT;
|
||||
|
||||
num_parents = clk_hw_get_num_parents(hw);
|
||||
for (i = 0; i < num_parents; i++) {
|
||||
if (cfg == rcg->parent_map[i].cfg) {
|
||||
if (src == rcg->parent_map[i].cfg) {
|
||||
f->src = rcg->parent_map[i].src;
|
||||
p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
|
||||
prate = clk_hw_get_rate(p);
|
||||
|
||||
@ -76,40 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_0[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_0[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DP_PHY_PLL_LINK_CLK, 1 },
|
||||
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
|
||||
{ .fw_name = "dp_phy_pll_vco_div_clk",
|
||||
.name = "dp_phy_pll_vco_div_clk"},
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
{ .fw_name = "dp_phy_pll_link_clk" },
|
||||
{ .fw_name = "dp_phy_pll_vco_div_clk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_2[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_2[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_byteclk",
|
||||
.name = "dsi0_phy_pll_out_byteclk" },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
@ -117,7 +109,6 @@ static const struct parent_map disp_cc_parent_map_3[] = {
|
||||
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
@ -125,32 +116,26 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
|
||||
{ .hw = &disp_cc_pll0.clkr.hw },
|
||||
{ .fw_name = "gcc_disp_gpll0_clk_src" },
|
||||
{ .hw = &disp_cc_pll0_out_even.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_4[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_GPLL0_OUT_MAIN, 4 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_4[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "gcc_disp_gpll0_clk_src" },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct parent_map disp_cc_parent_map_5[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data disp_cc_parent_data_5[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_dsiclk",
|
||||
.name = "dsi0_phy_pll_out_dsiclk" },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
|
||||
@ -169,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_ahb_clk_src",
|
||||
.parent_data = disp_cc_parent_data_4,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
@ -183,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_byte0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
@ -203,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_aux_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = 2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
@ -216,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
@ -230,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_byte2_ops,
|
||||
},
|
||||
@ -244,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk_src",
|
||||
.parent_data = disp_cc_parent_data_1,
|
||||
.num_parents = 4,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_dp_ops,
|
||||
},
|
||||
@ -259,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_2,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
@ -282,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -295,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_data = disp_cc_parent_data_5,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_pixel_ops,
|
||||
},
|
||||
@ -310,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk_src",
|
||||
.parent_data = disp_cc_parent_data_3,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
@ -324,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk_src",
|
||||
.parent_data = disp_cc_parent_data_0,
|
||||
.num_parents = 2,
|
||||
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -60,7 +60,6 @@ static const struct parent_map gpu_cc_parent_map_0[] = {
|
||||
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
||||
{ P_GPLL0_OUT_MAIN, 5 },
|
||||
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
@ -68,7 +67,6 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
||||
{ .hw = &gpu_cc_pll1.clkr.hw },
|
||||
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
|
||||
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
||||
@ -86,7 +84,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "gpu_cc_gmu_clk_src",
|
||||
.parent_data = gpu_cc_parent_data_0,
|
||||
.num_parents = 5,
|
||||
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
|
||||
@ -50,13 +50,11 @@ static struct clk_alpha_pll video_pll0 = {
|
||||
static const struct parent_map video_cc_parent_map_1[] = {
|
||||
{ P_BI_TCXO, 0 },
|
||||
{ P_VIDEO_PLL0_OUT_MAIN, 1 },
|
||||
{ P_CORE_BI_PLL_TEST_SE, 7 },
|
||||
};
|
||||
|
||||
static const struct clk_parent_data video_cc_parent_data_1[] = {
|
||||
{ .fw_name = "bi_tcxo" },
|
||||
{ .hw = &video_pll0.clkr.hw },
|
||||
{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
|
||||
};
|
||||
|
||||
static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = {
|
||||
@ -78,7 +76,7 @@ static struct clk_rcg2 video_cc_venus_clk_src = {
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "video_cc_venus_clk_src",
|
||||
.parent_data = video_cc_parent_data_1,
|
||||
.num_parents = 3,
|
||||
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
},
|
||||
|
||||
@ -6,6 +6,9 @@
|
||||
#ifndef __LINUX_OF_CLK_H
|
||||
#define __LINUX_OF_CLK_H
|
||||
|
||||
struct device_node;
|
||||
struct of_device_id;
|
||||
|
||||
#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF)
|
||||
|
||||
unsigned int of_clk_get_parent_count(struct device_node *np);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user