Merge remote-tracking branches 'asoc/fix/rt5640' and 'asoc/fix/wm8962' into asoc-linus
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8c0f551004
@ -359,7 +359,7 @@ static const DECLARE_TLV_DB_RANGE(bst_tlv,
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/* Interface data select */
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static const char * const rt5640_data_select[] = {
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"Normal", "left copy to right", "right copy to left", "Swap"};
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"Normal", "Swap", "left copy to right", "right copy to left"};
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static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
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RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
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@ -443,39 +443,39 @@
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#define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
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#define RT5640_IF1_DAC_SEL_SFT 14
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#define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
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#define RT5640_IF1_DAC_SEL_L2R (0x1 << 14)
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#define RT5640_IF1_DAC_SEL_R2L (0x2 << 14)
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#define RT5640_IF1_DAC_SEL_SWAP (0x3 << 14)
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#define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
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#define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
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#define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
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#define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
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#define RT5640_IF1_ADC_SEL_SFT 12
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#define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
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#define RT5640_IF1_ADC_SEL_L2R (0x1 << 12)
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#define RT5640_IF1_ADC_SEL_R2L (0x2 << 12)
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#define RT5640_IF1_ADC_SEL_SWAP (0x3 << 12)
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#define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
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#define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
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#define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
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#define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
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#define RT5640_IF2_DAC_SEL_SFT 10
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#define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
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#define RT5640_IF2_DAC_SEL_L2R (0x1 << 10)
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#define RT5640_IF2_DAC_SEL_R2L (0x2 << 10)
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#define RT5640_IF2_DAC_SEL_SWAP (0x3 << 10)
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#define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
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#define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
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#define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
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#define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
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#define RT5640_IF2_ADC_SEL_SFT 8
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#define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
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#define RT5640_IF2_ADC_SEL_L2R (0x1 << 8)
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#define RT5640_IF2_ADC_SEL_R2L (0x2 << 8)
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#define RT5640_IF2_ADC_SEL_SWAP (0x3 << 8)
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#define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
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#define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
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#define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
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#define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
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#define RT5640_IF3_DAC_SEL_SFT 6
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#define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
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#define RT5640_IF3_DAC_SEL_L2R (0x1 << 6)
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#define RT5640_IF3_DAC_SEL_R2L (0x2 << 6)
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#define RT5640_IF3_DAC_SEL_SWAP (0x3 << 6)
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#define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
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#define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
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#define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
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#define RT5640_IF3_ADC_SEL_MASK (0x3 << 4)
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#define RT5640_IF3_ADC_SEL_SFT 4
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#define RT5640_IF3_ADC_SEL_NOR (0x0 << 4)
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#define RT5640_IF3_ADC_SEL_L2R (0x1 << 4)
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#define RT5640_IF3_ADC_SEL_R2L (0x2 << 4)
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#define RT5640_IF3_ADC_SEL_SWAP (0x3 << 4)
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#define RT5640_IF3_ADC_SEL_SWAP (0x1 << 4)
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#define RT5640_IF3_ADC_SEL_L2R (0x2 << 4)
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#define RT5640_IF3_ADC_SEL_R2L (0x3 << 4)
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/* REC Left Mixer Control 1 (0x3b) */
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#define RT5640_G_HP_L_RM_L_MASK (0x7 << 13)
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@ -2471,7 +2471,7 @@ static void wm8962_configure_bclk(struct snd_soc_codec *codec)
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break;
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default:
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dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
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dspclk = wm8962->sysclk;
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dspclk = wm8962->sysclk_rate;
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}
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dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
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