Merge branch 'aquantia-fixes'
Igor Russkikh says: ==================== Aquantia/Marvell AQtion atlantic driver fixes 10/2019 Here is a set of various bugfixes, to be considered for stable as well. V2: double space removed ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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commit
8c16b55bbf
@ -194,9 +194,7 @@ static void aq_ndev_set_multicast_settings(struct net_device *ndev)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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aq_nic_set_packet_filter(aq_nic, ndev->flags);
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aq_nic_set_multicast_list(aq_nic, ndev);
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(void)aq_nic_set_multicast_list(aq_nic, ndev);
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}
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static int aq_ndo_vlan_rx_add_vid(struct net_device *ndev, __be16 proto,
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@ -631,9 +631,12 @@ err_exit:
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int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
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{
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unsigned int packet_filter = self->packet_filter;
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const struct aq_hw_ops *hw_ops = self->aq_hw_ops;
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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unsigned int packet_filter = ndev->flags;
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struct netdev_hw_addr *ha = NULL;
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unsigned int i = 0U;
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int err = 0;
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self->mc_list.count = 0;
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if (netdev_uc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
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@ -641,29 +644,26 @@ int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
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} else {
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netdev_for_each_uc_addr(ha, ndev) {
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ether_addr_copy(self->mc_list.ar[i++], ha->addr);
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if (i >= AQ_HW_MULTICAST_ADDRESS_MAX)
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break;
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}
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}
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if (i + netdev_mc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
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packet_filter |= IFF_ALLMULTI;
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} else {
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netdev_for_each_mc_addr(ha, ndev) {
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ether_addr_copy(self->mc_list.ar[i++], ha->addr);
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if (i >= AQ_HW_MULTICAST_ADDRESS_MAX)
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break;
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cfg->is_mc_list_enabled = !!(packet_filter & IFF_MULTICAST);
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if (cfg->is_mc_list_enabled) {
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if (i + netdev_mc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
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packet_filter |= IFF_ALLMULTI;
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} else {
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netdev_for_each_mc_addr(ha, ndev) {
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ether_addr_copy(self->mc_list.ar[i++],
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ha->addr);
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}
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}
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}
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if (i > 0 && i <= AQ_HW_MULTICAST_ADDRESS_MAX) {
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packet_filter |= IFF_MULTICAST;
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self->mc_list.count = i;
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self->aq_hw_ops->hw_multicast_list_set(self->aq_hw,
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self->mc_list.ar,
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self->mc_list.count);
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err = hw_ops->hw_multicast_list_set(self->aq_hw,
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self->mc_list.ar,
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self->mc_list.count);
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}
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return aq_nic_set_packet_filter(self, packet_filter);
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}
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@ -313,6 +313,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self,
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break;
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buff->is_error |= buff_->is_error;
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buff->is_cso_err |= buff_->is_cso_err;
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} while (!buff_->is_eop);
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@ -320,7 +321,7 @@ int aq_ring_rx_clean(struct aq_ring_s *self,
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err = 0;
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goto err_exit;
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}
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if (buff->is_error) {
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if (buff->is_error || buff->is_cso_err) {
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buff_ = buff;
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do {
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next_ = buff_->next,
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@ -818,14 +818,15 @@ static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
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cfg->is_vlan_force_promisc);
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hw_atl_rpfl2multicast_flr_en_set(self,
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IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
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IS_FILTER_ENABLED(IFF_ALLMULTI) &&
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IS_FILTER_ENABLED(IFF_MULTICAST), 0);
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hw_atl_rpfl2_accept_all_mc_packets_set(self,
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IS_FILTER_ENABLED(IFF_ALLMULTI));
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IS_FILTER_ENABLED(IFF_ALLMULTI) &&
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IS_FILTER_ENABLED(IFF_MULTICAST));
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hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
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cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
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for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
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hw_atl_rpfl2_uc_flr_en_set(self,
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@ -968,14 +969,26 @@ static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
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static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
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{
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int err;
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u32 val;
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hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
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/* Invalidate Descriptor Cache to prevent writing to the cached
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* descriptors and to the data pointer of those descriptors
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*/
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hw_atl_rdm_rx_dma_desc_cache_init_set(self, 1);
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hw_atl_rdm_rx_dma_desc_cache_init_tgl(self);
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return aq_hw_err_from_flags(self);
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err = aq_hw_err_from_flags(self);
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if (err)
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goto err_exit;
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readx_poll_timeout_atomic(hw_atl_rdm_rx_dma_desc_cache_init_done_get,
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self, val, val == 1, 1000U, 10000U);
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err_exit:
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return err;
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}
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static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
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@ -606,12 +606,25 @@ void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode
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HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
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}
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void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init)
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void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
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{
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u32 val;
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val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
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HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
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HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
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HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
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HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
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init);
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val ^ 1);
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}
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u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
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{
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return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
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RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
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RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
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}
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void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
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@ -313,8 +313,11 @@ void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
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u32 rx_pkt_buff_size_per_tc,
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u32 buffer);
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/* set rdm rx dma descriptor cache init */
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void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init);
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/* toggle rdm rx dma descriptor cache init */
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void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw);
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/* get rdm rx dma descriptor cache init done */
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u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw);
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/* set rx xoff enable (per tc) */
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void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
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@ -318,6 +318,25 @@
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/* default value of bitfield rdm_desc_init_i */
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#define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0
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/* rdm_desc_init_done_i bitfield definitions
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* preprocessor definitions for the bitfield rdm_desc_init_done_i.
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* port="pif_rdm_desc_init_done_i"
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*/
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/* register address for bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10
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/* bitmask for bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U
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/* inverted bitmask for bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe
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/* lower bit position of bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U
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/* width of bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1
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/* default value of bitfield rdm_desc_init_done_i */
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#define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0
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/* rx int_desc_wrb_en bitfield definitions
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* preprocessor definitions for the bitfield "int_desc_wrb_en".
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* port="pif_rdm_int_desc_wrb_en_i"
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@ -337,7 +337,7 @@ static int aq_fw2x_get_phy_temp(struct aq_hw_s *self, int *temp)
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/* Convert PHY temperature from 1/256 degree Celsius
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* to 1/1000 degree Celsius.
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*/
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*temp = temp_res * 1000 / 256;
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*temp = (temp_res & 0xFFFF) * 1000 / 256;
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return 0;
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}
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