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drm/nouveau/fifo: add chid_nr()

Browse Source 
- reads channel count from GPU from gm200 onwards
- removes gm20b/gp10b (they become identical to gm200/gp100)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2022-06-01 20:47:21 +10:00
parent 973b32443b
commit 8c18138c76
25 changed files with 114 additions and 137 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View File

@ -34,4 +34,5 @@ nvkm_blob_dtor(struct nvkm_blob *blob)
blob->data = NULL;
blob->size = 0;
}
#endif

2
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View File

@ -72,9 +72,7 @@ int gk208_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
int gk20a_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gm107_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gm200_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gm20b_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gp100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gp10b_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int gv100_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int tu102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);
int ga102_fifo_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fifo **);

4
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -2130,7 +2130,7 @@ nv12b_chipset = {
.volt = { 0x00000001, gm20b_volt_new },
.ce = { 0x00000004, gm200_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm20b_fifo_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = { 0x00000001, gm20b_gr_new },
.sw = { 0x00000001, gf100_sw_new },
};
@ -2356,7 +2356,7 @@ nv13b_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x00000001, gp100_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp10b_fifo_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp10b_gr_new },
.sw = { 0x00000001, gf100_sw_new },
};

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
View File

@ -13,9 +13,7 @@ nvkm-y += nvkm/engine/fifo/gk208.o
nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/gm107.o
nvkm-y += nvkm/engine/fifo/gm200.o
nvkm-y += nvkm/engine/fifo/gm20b.o
nvkm-y += nvkm/engine/fifo/gp100.o
nvkm-y += nvkm/engine/fifo/gp10b.o
nvkm-y += nvkm/engine/fifo/gv100.o
nvkm-y += nvkm/engine/fifo/tu102.o
nvkm-y += nvkm/engine/fifo/ga102.o

20
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View File

@ -24,14 +24,14 @@
#include "priv.h"
#include "chan.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <subdev/mc.h>
#include <nvif/event.h>
#include <nvif/cl0080.h>
#include <nvif/unpack.h>
#include "gk104.h"
void
nvkm_fifo_recover_chan(struct nvkm_fifo *fifo, int chid)
{
@ -290,25 +290,27 @@ nvkm_fifo = {
int
nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, int nr, struct nvkm_fifo *fifo)
enum nvkm_subdev_type type, int inst, struct nvkm_fifo *fifo)
{
int ret;
int ret, nr;
fifo->func = func;
INIT_LIST_HEAD(&fifo->chan);
spin_lock_init(&fifo->lock);
mutex_init(&fifo->mutex);
ret = nvkm_engine_ctor(&nvkm_fifo, device, type, inst, true, &fifo->engine);
if (ret)
return ret;
INIT_LIST_HEAD(&fifo->chan);
nr = func->chid_nr ? func->chid_nr(fifo) : gk104_fifo(fifo)->func->chid_nr(fifo);
if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR))
fifo->nr = NVKM_FIFO_CHID_NR;
else
fifo->nr = nr;
bitmap_clear(fifo->mask, 0, fifo->nr);
ret = nvkm_engine_ctor(&nvkm_fifo, device, type, inst, true, &fifo->engine);
if (ret)
return ret;
if (func->uevent_init) {
ret = nvkm_event_init(&nvkm_fifo_uevent_func, &fifo->engine.subdev, 1, 1,
&fifo->uevent);

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
View File

@ -110,6 +110,7 @@ static const struct nvkm_fifo_func
g84_fifo = {
.dtor = nv50_fifo_dtor,
.oneinit = nv50_fifo_oneinit,
.chid_nr = nv50_fifo_chid_nr,
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = g84_fifo_engine_id,

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -669,6 +669,7 @@ static const struct nvkm_fifo_func
gf100_fifo = {
.dtor = gf100_fifo_dtor,
.oneinit = gf100_fifo_oneinit,
.chid_nr = nv50_fifo_chid_nr,
.init = gf100_fifo_init,
.fini = gf100_fifo_fini,
.intr = gf100_fifo_intr,
@ -695,5 +696,5 @@ gf100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
INIT_WORK(&fifo->recover.work, gf100_fifo_recover_work);
*pfifo = &fifo->base;
return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, 128, &fifo->base);
return nvkm_fifo_ctor(&gf100_fifo, device, type, inst, &fifo->base);
}

11
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -1055,6 +1055,12 @@ gk104_fifo_init(struct nvkm_fifo *base)
nvkm_wr32(device, 0x002140, 0x7fffffff);
}
int
gk104_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 4096;
}
void *
gk104_fifo_dtor(struct nvkm_fifo *base)
{
@ -1103,7 +1109,7 @@ gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device,
INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work);
*pfifo = &fifo->base;
return nvkm_fifo_ctor(&gk104_fifo_, device, type, inst, nr, &fifo->base);
return nvkm_fifo_ctor(&gk104_fifo_, device, type, inst, &fifo->base);
}
const struct nvkm_enum
@ -1230,6 +1236,7 @@ gk104_fifo_fault_gpcclient[] = {
static const struct gk104_fifo_func
gk104_fifo = {
.chid_nr = gk104_fifo_chid_nr,
.intr.fault = gf100_fifo_intr_fault,
.pbdma = &gk104_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -1245,5 +1252,5 @@ int
gk104_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gk104_fifo, device, type, inst, 4096, pfifo);
return gk104_fifo_new_(&gk104_fifo, device, type, inst, 0, pfifo);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
View File

@ -46,6 +46,8 @@ struct gk104_fifo {
};
struct gk104_fifo_func {
int (*chid_nr)(struct nvkm_fifo *);
struct {
void (*fault)(struct nvkm_fifo *, int unit);
} intr;

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
View File

@ -48,6 +48,7 @@ gk110_fifo_runlist = {
static const struct gk104_fifo_func
gk110_fifo = {
.chid_nr = gk104_fifo_chid_nr,
.intr.fault = gf100_fifo_intr_fault,
.pbdma = &gk104_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -63,5 +64,5 @@ int
gk110_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gk110_fifo, device, type, inst, 4096, pfifo);
return gk104_fifo_new_(&gk110_fifo, device, type, inst, 0, pfifo);
}

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
View File

@ -43,8 +43,15 @@ gk208_fifo_pbdma = {
.init_timeout = gk208_fifo_pbdma_init_timeout,
};
static int
gk208_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 1024;
}
static const struct gk104_fifo_func
gk208_fifo = {
.chid_nr = gk208_fifo_chid_nr,
.intr.fault = gf100_fifo_intr_fault,
.pbdma = &gk208_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -60,5 +67,5 @@ int
gk208_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gk208_fifo, device, type, inst, 1024, pfifo);
return gk104_fifo_new_(&gk208_fifo, device, type, inst, 0, pfifo);
}

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
View File

@ -26,6 +26,7 @@
static const struct gk104_fifo_func
gk20a_fifo = {
.chid_nr = nv50_fifo_chid_nr,
.intr.fault = gf100_fifo_intr_fault,
.pbdma = &gk208_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -41,5 +42,5 @@ int
gk20a_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gk20a_fifo, device, type, inst, 128, pfifo);
return gk104_fifo_new_(&gk20a_fifo, device, type, inst, 0, pfifo);
}

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
View File

@ -92,8 +92,15 @@ gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
nvkm_fifo_fault(fifo, &info);
}
static int
gm107_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 2048;
}
static const struct gk104_fifo_func
gm107_fifo = {
.chid_nr = gm107_fifo_chid_nr,
.intr.fault = gm107_fifo_intr_fault,
.pbdma = &gk208_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -109,5 +116,5 @@ int
gm107_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gm107_fifo, device, type, inst, 2048, pfifo);
return gk104_fifo_new_(&gm107_fifo, device, type, inst, 0, pfifo);
}

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
View File

@ -40,8 +40,15 @@ gm200_fifo_pbdma = {
.init_timeout = gk208_fifo_pbdma_init_timeout,
};
int
gm200_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return nvkm_rd32(fifo->engine.subdev.device, 0x002008);
}
static const struct gk104_fifo_func
gm200_fifo = {
.chid_nr = gm200_fifo_chid_nr,
.intr.fault = gm107_fifo_intr_fault,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -57,5 +64,5 @@ int
gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gm200_fifo, device, type, inst, 4096, pfifo);
return gk104_fifo_new_(&gm200_fifo, device, type, inst, 0, pfifo);
}

45
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
View File

@ -1,45 +0,0 @@
/*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gk104.h"
#include "changk104.h"
#include <nvif/class.h>
static const struct gk104_fifo_func
gm20b_fifo = {
.intr.fault = gm107_fifo_intr_fault,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gm107_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.runlist = &gm107_fifo_runlist,
.chan = {{0,0,MAXWELL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },
};
int
gm20b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gm20b_fifo, device, type, inst, 512, pfifo);
}

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
View File

@ -78,6 +78,7 @@ gp100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
static const struct gk104_fifo_func
gp100_fifo = {
.chid_nr = gm200_fifo_chid_nr,
.intr.fault = gp100_fifo_intr_fault,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
@ -94,5 +95,5 @@ int
gp100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gp100_fifo, device, type, inst, 4096, pfifo);
return gk104_fifo_new_(&gp100_fifo, device, type, inst, 0, pfifo);
}

46
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c
View File

@ -1,46 +0,0 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gk104.h"
#include "changk104.h"
#include <nvif/class.h>
static const struct gk104_fifo_func
gp10b_fifo = {
.intr.fault = gp100_fifo_intr_fault,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gp100_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.runlist = &gm107_fifo_runlist,
.chan = {{0,0,PASCAL_CHANNEL_GPFIFO_A}, gk104_fifo_gpfifo_new },
.cgrp_force = true,
};
int
gp10b_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gp10b_fifo, device, type, inst, 512, pfifo);
}

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
View File

@ -287,6 +287,7 @@ gv100_fifo_fault_access[] = {
static const struct gk104_fifo_func
gv100_fifo = {
.chid_nr = gm200_fifo_chid_nr,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gv100_fifo_fault_access,
.fault.engine = gv100_fifo_fault_engine,
@ -302,5 +303,5 @@ int
gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
{
return gk104_fifo_new_(&gv100_fifo, device, type, inst, 4096, pfifo);
return gk104_fifo_new_(&gv100_fifo, device, type, inst, 0, pfifo);
}

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -356,6 +356,12 @@ nv04_fifo_init(struct nvkm_fifo *base)
nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
}
static int
nv04_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 16;
}
int
nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, int nr, const struct nv04_fifo_ramfc *ramfc,
@ -369,7 +375,7 @@ nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
fifo->ramfc = ramfc;
*pfifo = &fifo->base;
ret = nvkm_fifo_ctor(func, device, type, inst, nr, &fifo->base);
ret = nvkm_fifo_ctor(func, device, type, inst, &fifo->base);
if (ret)
return ret;
@ -379,6 +385,7 @@ nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
static const struct nvkm_fifo_func
nv04_fifo = {
.chid_nr = nv04_fifo_chid_nr,
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,

7
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
View File

@ -39,8 +39,15 @@ nv10_fifo_ramfc[] = {
{}
};
int
nv10_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 32;
}
static const struct nvkm_fifo_func
nv10_fifo = {
.chid_nr = nv10_fifo_chid_nr,
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View File

@ -79,6 +79,7 @@ nv17_fifo_init(struct nvkm_fifo *base)
static const struct nvkm_fifo_func
nv17_fifo = {
.chid_nr = nv10_fifo_chid_nr,
.init = nv17_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -110,6 +110,7 @@ nv40_fifo_init(struct nvkm_fifo *base)
static const struct nvkm_fifo_func
nv40_fifo = {
.chid_nr = nv10_fifo_chid_nr,
.init = nv40_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
View File

@ -96,6 +96,12 @@ nv50_fifo_init(struct nvkm_fifo *base)
nvkm_wr32(device, 0x002500, 0x00000001);
}
int
nv50_fifo_chid_nr(struct nvkm_fifo *fifo)
{
return 128;
}
void *
nv50_fifo_dtor(struct nvkm_fifo *base)
{
@ -116,7 +122,7 @@ nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
return -ENOMEM;
*pfifo = &fifo->base;
ret = nvkm_fifo_ctor(func, device, type, inst, 128, &fifo->base);
ret = nvkm_fifo_ctor(func, device, type, inst, &fifo->base);
if (ret)
return ret;
@ -129,6 +135,7 @@ static const struct nvkm_fifo_func
nv50_fifo = {
.dtor = nv50_fifo_dtor,
.oneinit = nv50_fifo_oneinit,
.chid_nr = nv50_fifo_chid_nr,
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,

15
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@ -4,8 +4,6 @@
#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
#include <engine/fifo.h>
int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
int nr, struct nvkm_fifo *);
void nvkm_fifo_uevent(struct nvkm_fifo *);
void nvkm_fifo_kevent(struct nvkm_fifo *, int chid);
void nvkm_fifo_recover_chan(struct nvkm_fifo *, int chid);
@ -16,7 +14,10 @@ nvkm_fifo_chan_inst_locked(struct nvkm_fifo *, u64 inst);
struct nvkm_fifo_chan_oclass;
struct nvkm_fifo_func {
void *(*dtor)(struct nvkm_fifo *);
int (*oneinit)(struct nvkm_fifo *);
int (*chid_nr)(struct nvkm_fifo *);
int (*info)(struct nvkm_fifo *, u64 mthd, u64 *data);
void (*init)(struct nvkm_fifo *);
void (*fini)(struct nvkm_fifo *);
@ -35,14 +36,24 @@ struct nvkm_fifo_func {
const struct nvkm_fifo_chan_oclass *chan[];
};
int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_fifo *);
void nv04_fifo_intr(struct nvkm_fifo *);
int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *nv04_fifo_id_engine(struct nvkm_fifo *, int);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
int nv10_fifo_chid_nr(struct nvkm_fifo *);
int nv50_fifo_chid_nr(struct nvkm_fifo *);
void gf100_fifo_intr_fault(struct nvkm_fifo *, int);
int gk104_fifo_chid_nr(struct nvkm_fifo *);
int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *gk104_fifo_id_engine(struct nvkm_fifo *, int);
int gm200_fifo_chid_nr(struct nvkm_fifo *);
#endif

33
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
View File

@ -24,12 +24,10 @@
#include "changk104.h"
#include <core/client.h>
#include <core/gpuobj.h>
#include <core/memory.h>
#include <subdev/bar.h>
#include <subdev/fault.h>
#include <subdev/top.h>
#include <subdev/timer.h>
#include <engine/sw.h>
#include <nvif/class.h>
@ -100,19 +98,6 @@ tu102_fifo_pbdma = {
.init_timeout = gk208_fifo_pbdma_init_timeout,
};
static const struct gk104_fifo_func
tu102_fifo = {
.pbdma = &tu102_fifo_pbdma,
.fault.access = gv100_fifo_fault_access,
.fault.engine = tu102_fifo_fault_engine,
.fault.reason = gv100_fifo_fault_reason,
.fault.hubclient = gv100_fifo_fault_hubclient,
.fault.gpcclient = gv100_fifo_fault_gpcclient,
.runlist = &tu102_fifo_runlist,
.chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
.cgrp_force = true,
};
static void
tu102_fifo_recover_work(struct work_struct *w)
{
@ -459,6 +444,20 @@ tu102_fifo_ = {
.class_new = gk104_fifo_class_new,
};
static const struct gk104_fifo_func
tu102_fifo = {
.chid_nr = gm200_fifo_chid_nr,
.pbdma = &tu102_fifo_pbdma,
.fault.access = gv100_fifo_fault_access,
.fault.engine = tu102_fifo_fault_engine,
.fault.reason = gv100_fifo_fault_reason,
.fault.hubclient = gv100_fifo_fault_hubclient,
.fault.gpcclient = gv100_fifo_fault_gpcclient,
.runlist = &tu102_fifo_runlist,
.chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
.cgrp_force = true,
};
int
tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_fifo **pfifo)
@ -471,5 +470,5 @@ tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
INIT_WORK(&fifo->recover.work, tu102_fifo_recover_work);
*pfifo = &fifo->base;
return nvkm_fifo_ctor(&tu102_fifo_, device, type, inst, 4096, &fifo->base);
return nvkm_fifo_ctor(&tu102_fifo_, device, type, inst, &fifo->base);
}