MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs
commit c7e814628df65f424fe197dde73bfc67e4a244d7 upstream. Use 64-bit accesses for 64-bit floating-point general registers with PTRACE_PEEKUSR, removing the truncation of their upper halves in the FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context access"), which inadvertently switched them to using 32-bit accesses. The PTRACE_POKEUSR side is fine as it's never been broken and continues using 64-bit accesses. Fixes: bbd426f542cb ("MIPS: Simplify FP context access") Signed-off-by: Maciej W. Rozycki <macro@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/19334/ Signed-off-by: James Hogan <jhogan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -841,7 +841,7 @@ long arch_ptrace(struct task_struct *child, long request,
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break;
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}
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#endif
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tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
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tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
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break;
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case PC:
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tmp = regs->cp0_epc;
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@ -107,7 +107,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
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addr & 1);
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break;
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}
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tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
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tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
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break;
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case PC:
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tmp = regs->cp0_epc;
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