KVM: arm64: Correct spelling of DBGDIDR register
The aarch32 debug ID register is called DBG*D*IDR (emphasis added), not DBGIDR, use the correct spelling. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210128132823.35067-1-alexandru.elisei@arm.com
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@ -1710,7 +1710,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
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{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
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};
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};
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static bool trap_dbgidr(struct kvm_vcpu *vcpu,
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static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p,
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struct sys_reg_params *p,
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const struct sys_reg_desc *r)
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const struct sys_reg_desc *r)
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{
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{
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@ -1757,8 +1757,8 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu,
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* guest. Revisit this one day, would this principle change.
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* guest. Revisit this one day, would this principle change.
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*/
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*/
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static const struct sys_reg_desc cp14_regs[] = {
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static const struct sys_reg_desc cp14_regs[] = {
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/* DBGIDR */
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/* DBGDIDR */
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{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
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{ Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
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/* DBGDTRRXext */
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/* DBGDTRRXext */
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{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
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{ Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
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