timbgpio: add support for interrupt triggering on both flanks
Introduce support for triggering interrupts on both rising and falling edge. This feature requires version 3 or newer of the IP, a version check is done when triggering on both edges is requested. Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -38,6 +38,8 @@
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#define TGPIO_ICR 0x14
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#define TGPIO_FLR 0x18
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#define TGPIO_LVR 0x1c
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#define TGPIO_VER 0x20
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#define TGPIO_BFLR 0x24
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struct timbgpio {
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void __iomem *membase;
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@ -126,17 +128,23 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
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struct timbgpio *tgpio = get_irq_chip_data(irq);
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int offset = irq - tgpio->irq_base;
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unsigned long flags;
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u32 lvr, flr;
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u32 lvr, flr, bflr = 0;
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u32 ver;
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if (offset < 0 || offset > tgpio->gpio.ngpio)
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return -EINVAL;
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ver = ioread32(tgpio->membase + TGPIO_VER);
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spin_lock_irqsave(&tgpio->lock, flags);
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lvr = ioread32(tgpio->membase + TGPIO_LVR);
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flr = ioread32(tgpio->membase + TGPIO_FLR);
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if (ver > 2)
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bflr = ioread32(tgpio->membase + TGPIO_BFLR);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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bflr &= ~(1 << offset);
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flr &= ~(1 << offset);
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if (trigger & IRQ_TYPE_LEVEL_HIGH)
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lvr |= 1 << offset;
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@ -144,21 +152,27 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
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lvr &= ~(1 << offset);
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}
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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else {
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if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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if (ver < 3)
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return -EINVAL;
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else {
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flr |= 1 << offset;
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bflr |= 1 << offset;
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}
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} else {
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bflr &= ~(1 << offset);
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flr |= 1 << offset;
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/* opposite compared to the datasheet, but it mirrors the
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* reality
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*/
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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lvr |= 1 << offset;
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else
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lvr &= ~(1 << offset);
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else
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lvr |= 1 << offset;
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}
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iowrite32(lvr, tgpio->membase + TGPIO_LVR);
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iowrite32(flr, tgpio->membase + TGPIO_FLR);
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if (ver > 2)
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iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
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iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
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spin_unlock_irqrestore(&tgpio->lock, flags);
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